Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
123 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
129 /* GPMC ecc engine settings for write */
130 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
145 struct nand_chip nand; member
170 /* fields specific for BCHx_HW ECC scheme */
172 /* NAND ready gpio */
178 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand); in mtd_to_omap()
182 * omap_prefetch_enable - configures and starts prefetch transfer
185 * @dma_mode: dma mode enable (1) or disable (0)
187 * @is_write: prefetch read(0) or write post(1) mode
195 return -1; in omap_prefetch_enable()
197 if (readl(info->reg.gpmc_prefetch_control)) in omap_prefetch_enable()
198 return -EBUSY; in omap_prefetch_enable()
201 writel(u32_count, info->reg.gpmc_prefetch_config2); in omap_prefetch_enable()
203 /* Set dma/mpu mode, the prefetch read / post write and in omap_prefetch_enable()
209 writel(val, info->reg.gpmc_prefetch_config1); in omap_prefetch_enable()
212 writel(0x1, info->reg.gpmc_prefetch_control); in omap_prefetch_enable()
218 * omap_prefetch_reset - disables and stops the prefetch engine
225 config1 = readl(info->reg.gpmc_prefetch_config1); in omap_prefetch_reset()
227 return -EINVAL; in omap_prefetch_reset()
230 writel(0x0, info->reg.gpmc_prefetch_control); in omap_prefetch_reset()
233 writel(0x0, info->reg.gpmc_prefetch_config1); in omap_prefetch_reset()
239 * omap_hwcontrol - hardware specific access to control-lines
240 * @chip: NAND chip object
243 * NAND_NCE: bit 0 -> don't care
244 * NAND_CLE: bit 1 -> Command Latch
245 * NAND_ALE: bit 2 -> Address Latch
255 writeb(cmd, info->reg.gpmc_nand_command); in omap_hwcontrol()
258 writeb(cmd, info->reg.gpmc_nand_address); in omap_hwcontrol()
261 writeb(cmd, info->reg.gpmc_nand_data); in omap_hwcontrol()
266 * omap_read_buf8 - read data from NAND controller into buffer
273 struct nand_chip *nand = mtd_to_nand(mtd); in omap_read_buf8() local
275 ioread8_rep(nand->legacy.IO_ADDR_R, buf, len); in omap_read_buf8()
279 * omap_write_buf8 - write buffer to NAND controller
290 while (len--) { in omap_write_buf8()
291 iowrite8(*p++, info->nand.legacy.IO_ADDR_W); in omap_write_buf8()
294 status = info->ops->nand_writebuffer_empty(); in omap_write_buf8()
300 * omap_read_buf16 - read data from NAND controller into buffer
307 struct nand_chip *nand = mtd_to_nand(mtd); in omap_read_buf16() local
309 ioread16_rep(nand->legacy.IO_ADDR_R, buf, len / 2); in omap_read_buf16()
313 * omap_write_buf16 - write buffer to NAND controller
326 while (len--) { in omap_write_buf16()
327 iowrite16(*p++, info->nand.legacy.IO_ADDR_W); in omap_write_buf16()
330 status = info->ops->nand_writebuffer_empty(); in omap_write_buf16()
336 * omap_read_buf_pref - read data from NAND controller into buffer
337 * @chip: NAND chip object
351 if (info->nand.options & NAND_BUSWIDTH_16) in omap_read_buf_pref()
356 len -= len % 4; in omap_read_buf_pref()
360 ret = omap_prefetch_enable(info->gpmc_cs, in omap_read_buf_pref()
364 if (info->nand.options & NAND_BUSWIDTH_16) in omap_read_buf_pref()
370 r_count = readl(info->reg.gpmc_prefetch_status); in omap_read_buf_pref()
373 ioread32_rep(info->nand.legacy.IO_ADDR_R, p, r_count); in omap_read_buf_pref()
375 len -= r_count << 2; in omap_read_buf_pref()
378 omap_prefetch_reset(info->gpmc_cs, info); in omap_read_buf_pref()
383 * omap_write_buf_pref - write buffer to NAND controller
384 * @chip: NAND chip object
401 writeb(*buf, info->nand.legacy.IO_ADDR_W); in omap_write_buf_pref()
403 len--; in omap_write_buf_pref()
407 ret = omap_prefetch_enable(info->gpmc_cs, in omap_write_buf_pref()
411 if (info->nand.options & NAND_BUSWIDTH_16) in omap_write_buf_pref()
417 w_count = readl(info->reg.gpmc_prefetch_status); in omap_write_buf_pref()
420 for (i = 0; (i < w_count) && len; i++, len -= 2) in omap_write_buf_pref()
421 iowrite16(*p++, info->nand.legacy.IO_ADDR_W); in omap_write_buf_pref()
423 /* wait for data to flushed-out before reset the prefetch */ in omap_write_buf_pref()
429 val = readl(info->reg.gpmc_prefetch_status); in omap_write_buf_pref()
434 omap_prefetch_reset(info->gpmc_cs, info); in omap_write_buf_pref()
471 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
473 dev_err(&info->pdev->dev, in omap_nand_dma_transfer()
478 tx = dmaengine_prep_slave_sg(info->dma, &sg, n, in omap_nand_dma_transfer()
484 tx->callback = omap_nand_dma_callback; in omap_nand_dma_transfer()
485 tx->callback_param = &info->comp; in omap_nand_dma_transfer()
488 init_completion(&info->comp); in omap_nand_dma_transfer()
491 dma_async_issue_pending(info->dma); in omap_nand_dma_transfer()
494 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_dma_transfer()
500 wait_for_completion(&info->comp); in omap_nand_dma_transfer()
506 val = readl(info->reg.gpmc_prefetch_status); in omap_nand_dma_transfer()
511 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_dma_transfer()
513 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
517 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
519 if (info->nand.options & NAND_BUSWIDTH_16) in omap_nand_dma_transfer()
529 * omap_read_buf_dma_pref - read data from NAND controller into buffer
530 * @chip: NAND chip object
539 if (len <= mtd->oobsize) in omap_read_buf_dma_pref()
542 /* start transfer in DMA mode */ in omap_read_buf_dma_pref()
547 * omap_write_buf_dma_pref - write buffer to NAND controller
548 * @chip: NAND chip object
557 if (len <= mtd->oobsize) in omap_write_buf_dma_pref()
560 /* start transfer in DMA mode */ in omap_write_buf_dma_pref()
565 * omap_nand_irq - GPMC irq handler
574 bytes = readl(info->reg.gpmc_prefetch_status); in omap_nand_irq()
577 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ in omap_nand_irq()
578 if (this_irq == info->gpmc_irq_count) in omap_nand_irq()
581 if (info->buf_len && (info->buf_len < bytes)) in omap_nand_irq()
582 bytes = info->buf_len; in omap_nand_irq()
583 else if (!info->buf_len) in omap_nand_irq()
585 iowrite32_rep(info->nand.legacy.IO_ADDR_W, (u32 *)info->buf, in omap_nand_irq()
587 info->buf = info->buf + bytes; in omap_nand_irq()
588 info->buf_len -= bytes; in omap_nand_irq()
591 ioread32_rep(info->nand.legacy.IO_ADDR_R, (u32 *)info->buf, in omap_nand_irq()
593 info->buf = info->buf + bytes; in omap_nand_irq()
595 if (this_irq == info->gpmc_irq_count) in omap_nand_irq()
602 complete(&info->comp); in omap_nand_irq()
604 disable_irq_nosync(info->gpmc_irq_fifo); in omap_nand_irq()
605 disable_irq_nosync(info->gpmc_irq_count); in omap_nand_irq()
611 * omap_read_buf_irq_pref - read data from NAND controller into buffer
612 * @chip: NAND chip object
623 if (len <= mtd->oobsize) { in omap_read_buf_irq_pref()
628 info->iomode = OMAP_NAND_IO_READ; in omap_read_buf_irq_pref()
629 info->buf = buf; in omap_read_buf_irq_pref()
630 init_completion(&info->comp); in omap_read_buf_irq_pref()
633 ret = omap_prefetch_enable(info->gpmc_cs, in omap_read_buf_irq_pref()
639 info->buf_len = len; in omap_read_buf_irq_pref()
641 enable_irq(info->gpmc_irq_count); in omap_read_buf_irq_pref()
642 enable_irq(info->gpmc_irq_fifo); in omap_read_buf_irq_pref()
645 wait_for_completion(&info->comp); in omap_read_buf_irq_pref()
648 omap_prefetch_reset(info->gpmc_cs, info); in omap_read_buf_irq_pref()
652 if (info->nand.options & NAND_BUSWIDTH_16) in omap_read_buf_irq_pref()
659 * omap_write_buf_irq_pref - write buffer to NAND controller
660 * @chip: NAND chip object
673 if (len <= mtd->oobsize) { in omap_write_buf_irq_pref()
678 info->iomode = OMAP_NAND_IO_WRITE; in omap_write_buf_irq_pref()
679 info->buf = (u_char *) buf; in omap_write_buf_irq_pref()
680 init_completion(&info->comp); in omap_write_buf_irq_pref()
683 ret = omap_prefetch_enable(info->gpmc_cs, in omap_write_buf_irq_pref()
689 info->buf_len = len; in omap_write_buf_irq_pref()
691 enable_irq(info->gpmc_irq_count); in omap_write_buf_irq_pref()
692 enable_irq(info->gpmc_irq_fifo); in omap_write_buf_irq_pref()
695 wait_for_completion(&info->comp); in omap_write_buf_irq_pref()
697 /* wait for data to flushed-out before reset the prefetch */ in omap_write_buf_irq_pref()
701 val = readl(info->reg.gpmc_prefetch_status); in omap_write_buf_irq_pref()
707 omap_prefetch_reset(info->gpmc_cs, info); in omap_write_buf_irq_pref()
711 if (info->nand.options & NAND_BUSWIDTH_16) in omap_write_buf_irq_pref()
718 * gen_true_ecc - This function will generate true ECC value
719 * @ecc_buf: buffer to store ecc code
721 * This generated true ECC value can be used when correcting
722 * data read from NAND flash memory core
738 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
739 * @ecc_data1: ecc code from nand spare area
740 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
743 * This function compares two ECC's and indicates if there is an error.
746 * was corrected, %1 is returned. Otherwise, %-1 is returned.
748 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ in omap_compare_ecc()
819 * ECC values are equal in omap_compare_ecc()
825 pr_debug("ECC UNCORRECTED_ERROR 1\n"); in omap_compare_ecc()
826 return -EBADMSG; in omap_compare_ecc()
829 /* UN-Correctable error */ in omap_compare_ecc()
830 pr_debug("ECC UNCORRECTED_ERROR B\n"); in omap_compare_ecc()
831 return -EBADMSG; in omap_compare_ecc()
847 pr_debug("Correcting single bit ECC error at offset: " in omap_compare_ecc()
861 return -EBADMSG; in omap_compare_ecc()
866 * omap_correct_data - Compares the ECC read with HW generated ECC
867 * @chip: NAND chip object
869 * @read_ecc: ecc read from nand flash
870 * @calc_ecc: ecc read from HW ECC registers
872 * Compares the ecc read from nand spare area with ECC registers values
873 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
876 * corrected errors is returned. If uncorrectable errors exist, %-1 is
887 if ((info->nand.ecc.mode == NAND_ECC_HW) && in omap_correct_data()
888 (info->nand.ecc.size == 2048)) in omap_correct_data()
909 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
910 * @chip: NAND chip object
911 * @dat: The pointer to data on which ecc is computed
914 * Using noninverted ECC can be considered ugly since writing a blank
915 * page ie. padding will clear the ECC bytes. This is no problem as long
917 * an erased page will produce an ECC mismatch between generated and read
918 * ECC bytes that has to be dealt with separately.
926 val = readl(info->reg.gpmc_ecc_config); in omap_calculate_ecc()
927 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) in omap_calculate_ecc()
928 return -EINVAL; in omap_calculate_ecc()
930 /* read ecc result */ in omap_calculate_ecc()
931 val = readl(info->reg.gpmc_ecc1_result); in omap_calculate_ecc()
941 * omap_enable_hwecc - This function enables the hardware ecc functionality
943 * @mode: Read/Write mode
945 static void omap_enable_hwecc(struct nand_chip *chip, int mode) in omap_enable_hwecc() argument
948 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; in omap_enable_hwecc()
951 /* clear ecc and enable bits */ in omap_enable_hwecc()
953 writel(val, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
955 /* program ecc and result sizes */ in omap_enable_hwecc()
956 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | in omap_enable_hwecc()
958 writel(val, info->reg.gpmc_ecc_size_config); in omap_enable_hwecc()
960 switch (mode) { in omap_enable_hwecc()
963 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
966 writel(ECCCLEAR, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
969 dev_info(&info->pdev->dev, in omap_enable_hwecc()
970 "error: unrecognized Mode[%d]!\n", mode); in omap_enable_hwecc()
974 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ in omap_enable_hwecc()
975 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); in omap_enable_hwecc()
976 writel(val, info->reg.gpmc_ecc_config); in omap_enable_hwecc()
980 * omap_wait - wait until the command is done
981 * @this: NAND Chip structure
984 * the way it is called from MTD layer, we should wait till the NAND
988 * general NAND and SmartMedia specs
998 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); in omap_wait()
1000 status = readb(info->reg.gpmc_nand_data); in omap_wait()
1006 status = readb(info->reg.gpmc_nand_data); in omap_wait()
1011 * omap_dev_ready - checks the NAND Ready GPIO line
1020 return gpiod_get_value(info->ready_gpiod); in omap_dev_ready()
1024 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1026 * @mode: Read/Write mode
1029 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1035 int mode) in omap_enable_hwecc_bch() argument
1040 enum omap_ecc ecc_opt = info->ecc_opt; in omap_enable_hwecc_bch()
1044 /* GPMC configurations for calculating ECC */ in omap_enable_hwecc_bch()
1055 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
1056 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
1075 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
1076 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
1088 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
1089 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
1091 ecc_size0 = 52; /* ECC bits in nibbles per sector */ in omap_enable_hwecc_bch()
1092 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ in omap_enable_hwecc_bch()
1103 writel(ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc_bch()
1105 /* Configure ecc size for BCH */ in omap_enable_hwecc_bch()
1107 writel(val, info->reg.gpmc_ecc_size_config); in omap_enable_hwecc_bch()
1109 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; in omap_enable_hwecc_bch()
1114 (wr_mode << 8) | /* wrap mode */ in omap_enable_hwecc_bch()
1116 (((nsectors-1) & 0x7) << 4) | /* number of sectors */ in omap_enable_hwecc_bch()
1117 (info->gpmc_cs << 1) | /* ECC CS */ in omap_enable_hwecc_bch()
1118 (0x1)); /* enable ECC */ in omap_enable_hwecc_bch()
1120 writel(val, info->reg.gpmc_ecc_config); in omap_enable_hwecc_bch()
1122 /* Clear ecc and enable bits */ in omap_enable_hwecc_bch()
1123 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc_bch()
1131 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1133 * @dat: The pointer to data on which ecc is computed
1137 * Support calculating of BCH4/8/16 ECC vectors for one sector
1144 int eccbytes = info->nand.ecc.bytes; in _omap_calculate_ecc_bch()
1145 struct gpmc_nand_regs *gpmc_regs = &info->reg; in _omap_calculate_ecc_bch()
1152 switch (info->ecc_opt) { in _omap_calculate_ecc_bch()
1155 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1156 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1157 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); in _omap_calculate_ecc_bch()
1158 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); in _omap_calculate_ecc_bch()
1175 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1176 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1187 val = readl(gpmc_regs->gpmc_bch_result6[i]); in _omap_calculate_ecc_bch()
1190 val = readl(gpmc_regs->gpmc_bch_result5[i]); in _omap_calculate_ecc_bch()
1195 val = readl(gpmc_regs->gpmc_bch_result4[i]); in _omap_calculate_ecc_bch()
1200 val = readl(gpmc_regs->gpmc_bch_result3[i]); in _omap_calculate_ecc_bch()
1205 val = readl(gpmc_regs->gpmc_bch_result2[i]); in _omap_calculate_ecc_bch()
1210 val = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1215 val = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1222 return -EINVAL; in _omap_calculate_ecc_bch()
1225 /* ECC scheme specific syndrome customizations */ in _omap_calculate_ecc_bch()
1226 switch (info->ecc_opt) { in _omap_calculate_ecc_bch()
1229 * ECC of blank pages results in 0x0 on reading back in _omap_calculate_ecc_bch()
1235 /* Set 8th ECC byte as 0x0 for ROM compatibility */ in _omap_calculate_ecc_bch()
1236 ecc_calc[eccbytes - 1] = 0x0; in _omap_calculate_ecc_bch()
1240 * ECC of blank pages results in 0x0 on reading back in _omap_calculate_ecc_bch()
1246 /* Set 14th ECC byte as 0x0 for ROM compatibility */ in _omap_calculate_ecc_bch()
1247 ecc_calc[eccbytes - 1] = 0x0; in _omap_calculate_ecc_bch()
1252 return -EINVAL; in _omap_calculate_ecc_bch()
1259 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1260 * @chip: NAND chip object
1261 * @dat: The pointer to data on which ecc is computed
1264 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1265 * when SW based correction is required as ECC is required for one sector
1275 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1277 * @dat: The pointer to data on which ecc is computed
1280 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1286 int eccbytes = info->nand.ecc.bytes; in omap_calculate_ecc_bch_multi()
1290 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; in omap_calculate_ecc_bch_multi()
1303 * erased_sector_bitflips - count bit flips
1317 for (i = 0; i < info->nand.ecc.size; i++) { in erased_sector_bitflips()
1319 if (flip_bits > info->nand.ecc.strength) in erased_sector_bitflips()
1323 for (i = 0; i < info->nand.ecc.bytes - 1; i++) { in erased_sector_bitflips()
1325 if (flip_bits > info->nand.ecc.strength) in erased_sector_bitflips()
1334 memset(data, 0xFF, info->nand.ecc.size); in erased_sector_bitflips()
1335 memset(oob, 0xFF, info->nand.ecc.bytes); in erased_sector_bitflips()
1342 * omap_elm_correct_data - corrects page data area in case error reported
1343 * @chip: NAND chip object
1345 * @read_ecc: ecc read from nand flash
1346 * @calc_ecc: ecc read from HW ECC registers
1348 * Calculated ecc vector reported as zero in case of non-error pages.
1349 * In case of non-zero ecc vector, first filter out erased-pages, and
1350 * then process data via ELM to detect bit-flips.
1356 struct nand_ecc_ctrl *ecc = &info->nand.ecc; in omap_elm_correct_data() local
1357 int eccsteps = info->nand.ecc.steps; in omap_elm_correct_data()
1370 switch (info->ecc_opt) { in omap_elm_correct_data()
1372 /* omit 7th ECC byte reserved for ROM code compatibility */ in omap_elm_correct_data()
1373 actual_eccbytes = ecc->bytes - 1; in omap_elm_correct_data()
1377 /* omit 14th ECC byte reserved for ROM code compatibility */ in omap_elm_correct_data()
1378 actual_eccbytes = ecc->bytes - 1; in omap_elm_correct_data()
1382 actual_eccbytes = ecc->bytes; in omap_elm_correct_data()
1386 dev_err(&info->pdev->dev, "invalid driver configuration\n"); in omap_elm_correct_data()
1387 return -EINVAL; in omap_elm_correct_data()
1398 * In case of error, non zero ecc reported. in omap_elm_correct_data()
1402 eccflag = 1; /* non zero ecc, error present */ in omap_elm_correct_data()
1411 * calc_ecc[] matches pattern for ECC(all 0xff) in omap_elm_correct_data()
1412 * so this is definitely an erased-page in omap_elm_correct_data()
1415 buf = &data[info->nand.ecc.size * i]; in omap_elm_correct_data()
1417 * count number of 0-bits in read_buf. in omap_elm_correct_data()
1419 * check is introduced in generic NAND driver in omap_elm_correct_data()
1425 * number of 0-bits within ECC limits in omap_elm_correct_data()
1426 * So this may be an erased-page in omap_elm_correct_data()
1431 * Too many 0-bits. It may be a in omap_elm_correct_data()
1432 * - programmed-page, OR in omap_elm_correct_data()
1433 * - erased-page with many bit-flips in omap_elm_correct_data()
1442 /* Update the ecc vector */ in omap_elm_correct_data()
1443 calc_ecc += ecc->bytes; in omap_elm_correct_data()
1444 read_ecc += ecc->bytes; in omap_elm_correct_data()
1452 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); in omap_elm_correct_data()
1457 dev_err(&info->pdev->dev, in omap_elm_correct_data()
1458 "uncorrectable bit-flips found\n"); in omap_elm_correct_data()
1459 err = -EBADMSG; in omap_elm_correct_data()
1462 switch (info->ecc_opt) { in omap_elm_correct_data()
1473 return -EINVAL; in omap_elm_correct_data()
1475 error_max = (ecc->size + actual_eccbytes) * 8; in omap_elm_correct_data()
1480 byte_pos = (error_max - pos - 1) / 8; in omap_elm_correct_data()
1489 (byte_pos - 512), in omap_elm_correct_data()
1490 spare_ecc[byte_pos - 512]); in omap_elm_correct_data()
1491 spare_ecc[byte_pos - 512] ^= in omap_elm_correct_data()
1495 dev_err(&info->pdev->dev, in omap_elm_correct_data()
1496 "invalid bit-flip @ %d:%d\n", in omap_elm_correct_data()
1498 err = -EBADMSG; in omap_elm_correct_data()
1507 data += ecc->size; in omap_elm_correct_data()
1508 spare_ecc += ecc->bytes; in omap_elm_correct_data()
1515 * omap_write_page_bch - BCH ecc based write page function for entire page
1516 * @chip: nand chip info structure
1518 * @oob_required: must write chip->oob_poi to OOB
1528 uint8_t *ecc_calc = chip->ecc.calc_buf; in omap_write_page_bch()
1532 /* Enable GPMC ecc engine */ in omap_write_page_bch()
1533 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in omap_write_page_bch()
1536 chip->legacy.write_buf(chip, buf, mtd->writesize); in omap_write_page_bch()
1538 /* Update ecc vector from GPMC result registers */ in omap_write_page_bch()
1541 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in omap_write_page_bch()
1542 chip->ecc.total); in omap_write_page_bch()
1546 /* Write ecc vector to OOB area */ in omap_write_page_bch()
1547 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); in omap_write_page_bch()
1553 * omap_write_subpage_bch - BCH hardware ECC based subpage write
1554 * @chip: nand chip info structure
1558 * @oob_required: must write chip->oob_poi to OOB
1568 u8 *ecc_calc = chip->ecc.calc_buf; in omap_write_subpage_bch()
1569 int ecc_size = chip->ecc.size; in omap_write_subpage_bch()
1570 int ecc_bytes = chip->ecc.bytes; in omap_write_subpage_bch()
1571 int ecc_steps = chip->ecc.steps; in omap_write_subpage_bch()
1573 u32 end_step = (offset + data_len - 1) / ecc_size; in omap_write_subpage_bch()
1578 * as ECC is calculated by hardware. in omap_write_subpage_bch()
1579 * ECC is calculated for all subpages but we choose in omap_write_subpage_bch()
1584 /* Enable GPMC ECC engine */ in omap_write_subpage_bch()
1585 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in omap_write_subpage_bch()
1588 chip->legacy.write_buf(chip, buf, mtd->writesize); in omap_write_subpage_bch()
1591 /* mask ECC of un-touched subpages by padding 0xFF */ in omap_write_subpage_bch()
1604 /* copy calculated ECC for whole page to chip->buffer->oob */ in omap_write_subpage_bch()
1605 /* this include masked-value(0xFF) for unwritten subpages */ in omap_write_subpage_bch()
1606 ecc_calc = chip->ecc.calc_buf; in omap_write_subpage_bch()
1607 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in omap_write_subpage_bch()
1608 chip->ecc.total); in omap_write_subpage_bch()
1612 /* write OOB buffer to NAND device */ in omap_write_subpage_bch()
1613 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); in omap_write_subpage_bch()
1619 * omap_read_page_bch - BCH ecc based page read function for entire page
1620 * @chip: nand chip info structure
1622 * @oob_required: caller requires OOB data read to chip->oob_poi
1625 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1629 * ecc engine enabled. ecc vector updated after read of OOB data.
1630 * For non error pages ecc vector reported as zero.
1636 uint8_t *ecc_calc = chip->ecc.calc_buf; in omap_read_page_bch()
1637 uint8_t *ecc_code = chip->ecc.code_buf; in omap_read_page_bch()
1643 /* Enable GPMC ecc engine */ in omap_read_page_bch()
1644 chip->ecc.hwctl(chip, NAND_ECC_READ); in omap_read_page_bch()
1647 chip->legacy.read_buf(chip, buf, mtd->writesize); in omap_read_page_bch()
1651 mtd->writesize + BADBLOCK_MARKER_LENGTH, in omap_read_page_bch()
1652 chip->oob_poi + BADBLOCK_MARKER_LENGTH, in omap_read_page_bch()
1653 chip->ecc.total, false); in omap_read_page_bch()
1655 /* Calculate ecc bytes */ in omap_read_page_bch()
1658 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in omap_read_page_bch()
1659 chip->ecc.total); in omap_read_page_bch()
1663 stat = chip->ecc.correct(chip, buf, ecc_code, ecc_calc); in omap_read_page_bch()
1666 mtd->ecc_stats.failed++; in omap_read_page_bch()
1668 mtd->ecc_stats.corrected += stat; in omap_read_page_bch()
1676 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1677 * @omap_nand_info: NAND device structure containing platform data
1684 /* check whether elm-id is passed via DT */ in is_elm_present()
1686 dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); in is_elm_present()
1692 dev_err(&info->pdev->dev, "ELM device not found\n"); in is_elm_present()
1696 info->elm_dev = &pdev->dev; in is_elm_present()
1704 switch (info->ecc_opt) { in omap2_nand_ecc_check()
1726 dev_err(&info->pdev->dev, in omap2_nand_ecc_check()
1731 dev_err(&info->pdev->dev, in omap2_nand_ecc_check()
1735 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) { in omap2_nand_ecc_check()
1736 dev_err(&info->pdev->dev, "ELM not available\n"); in omap2_nand_ecc_check()
1744 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1746 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1747 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1752 struct device_node *child = dev->of_node; in omap_get_dt_info()
1759 return -EINVAL; in omap_get_dt_info()
1762 info->gpmc_cs = cs; in omap_get_dt_info()
1764 /* detect availability of ELM module. Won't be present pre-OMAP4 */ in omap_get_dt_info()
1765 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); in omap_get_dt_info()
1766 if (!info->elm_of_node) { in omap_get_dt_info()
1767 info->elm_of_node = of_parse_phandle(child, "elm_id", 0); in omap_get_dt_info()
1768 if (!info->elm_of_node) in omap_get_dt_info()
1769 dev_dbg(dev, "ti,elm-id not in DT\n"); in omap_get_dt_info()
1772 /* select ecc-scheme for NAND */ in omap_get_dt_info()
1773 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { in omap_get_dt_info()
1774 dev_err(dev, "ti,nand-ecc-opt not found\n"); in omap_get_dt_info()
1775 return -EINVAL; in omap_get_dt_info()
1779 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW; in omap_get_dt_info()
1781 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) { in omap_get_dt_info()
1782 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW; in omap_get_dt_info()
1784 if (info->elm_of_node) in omap_get_dt_info()
1785 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW; in omap_get_dt_info()
1787 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; in omap_get_dt_info()
1789 if (info->elm_of_node) in omap_get_dt_info()
1790 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW; in omap_get_dt_info()
1792 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; in omap_get_dt_info()
1794 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW; in omap_get_dt_info()
1796 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n"); in omap_get_dt_info()
1797 return -EINVAL; in omap_get_dt_info()
1800 /* select data transfer mode */ in omap_get_dt_info()
1801 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) { in omap_get_dt_info()
1804 info->xfer_type = i; in omap_get_dt_info()
1809 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n"); in omap_get_dt_info()
1810 return -EINVAL; in omap_get_dt_info()
1820 struct nand_chip *chip = &info->nand; in omap_ooblayout_ecc()
1823 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && in omap_ooblayout_ecc()
1824 !(chip->options & NAND_BUSWIDTH_16)) in omap_ooblayout_ecc()
1828 return -ERANGE; in omap_ooblayout_ecc()
1830 oobregion->offset = off; in omap_ooblayout_ecc()
1831 oobregion->length = chip->ecc.total; in omap_ooblayout_ecc()
1840 struct nand_chip *chip = &info->nand; in omap_ooblayout_free()
1843 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && in omap_ooblayout_free()
1844 !(chip->options & NAND_BUSWIDTH_16)) in omap_ooblayout_free()
1848 return -ERANGE; in omap_ooblayout_free()
1850 off += chip->ecc.total; in omap_ooblayout_free()
1851 if (off >= mtd->oobsize) in omap_ooblayout_free()
1852 return -ERANGE; in omap_ooblayout_free()
1854 oobregion->offset = off; in omap_ooblayout_free()
1855 oobregion->length = mtd->oobsize - off; in omap_ooblayout_free()
1861 .ecc = omap_ooblayout_ecc,
1871 if (section >= chip->ecc.steps) in omap_sw_ooblayout_ecc()
1872 return -ERANGE; in omap_sw_ooblayout_ecc()
1876 * reserved after each ECC step. in omap_sw_ooblayout_ecc()
1878 oobregion->offset = off + (section * (chip->ecc.bytes + 1)); in omap_sw_ooblayout_ecc()
1879 oobregion->length = chip->ecc.bytes; in omap_sw_ooblayout_ecc()
1891 return -ERANGE; in omap_sw_ooblayout_free()
1895 * reserved after each ECC step. in omap_sw_ooblayout_free()
1897 off += ((chip->ecc.bytes + 1) * chip->ecc.steps); in omap_sw_ooblayout_free()
1898 if (off >= mtd->oobsize) in omap_sw_ooblayout_free()
1899 return -ERANGE; in omap_sw_ooblayout_free()
1901 oobregion->offset = off; in omap_sw_ooblayout_free()
1902 oobregion->length = mtd->oobsize - off; in omap_sw_ooblayout_free()
1908 .ecc = omap_sw_ooblayout_ecc,
1916 struct device *dev = &info->pdev->dev; in omap_nand_attach_chip()
1922 if (chip->bbt_options & NAND_BBT_USE_FLASH) in omap_nand_attach_chip()
1923 chip->bbt_options |= NAND_BBT_NO_OOB; in omap_nand_attach_chip()
1925 chip->options |= NAND_SKIP_BBTSCAN; in omap_nand_attach_chip()
1927 /* Re-populate low-level callbacks based on xfer modes */ in omap_nand_attach_chip()
1928 switch (info->xfer_type) { in omap_nand_attach_chip()
1930 chip->legacy.read_buf = omap_read_buf_pref; in omap_nand_attach_chip()
1931 chip->legacy.write_buf = omap_write_buf_pref; in omap_nand_attach_chip()
1941 info->dma = dma_request_chan(dev->parent, "rxtx"); in omap_nand_attach_chip()
1943 if (IS_ERR(info->dma)) { in omap_nand_attach_chip()
1945 return PTR_ERR(info->dma); in omap_nand_attach_chip()
1950 cfg.src_addr = info->phys_base; in omap_nand_attach_chip()
1951 cfg.dst_addr = info->phys_base; in omap_nand_attach_chip()
1956 err = dmaengine_slave_config(info->dma, &cfg); in omap_nand_attach_chip()
1963 chip->legacy.read_buf = omap_read_buf_dma_pref; in omap_nand_attach_chip()
1964 chip->legacy.write_buf = omap_write_buf_dma_pref; in omap_nand_attach_chip()
1969 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0); in omap_nand_attach_chip()
1970 if (info->gpmc_irq_fifo <= 0) { in omap_nand_attach_chip()
1972 return -ENODEV; in omap_nand_attach_chip()
1974 err = devm_request_irq(dev, info->gpmc_irq_fifo, in omap_nand_attach_chip()
1976 "gpmc-nand-fifo", info); in omap_nand_attach_chip()
1979 info->gpmc_irq_fifo, err); in omap_nand_attach_chip()
1980 info->gpmc_irq_fifo = 0; in omap_nand_attach_chip()
1984 info->gpmc_irq_count = platform_get_irq(info->pdev, 1); in omap_nand_attach_chip()
1985 if (info->gpmc_irq_count <= 0) { in omap_nand_attach_chip()
1987 return -ENODEV; in omap_nand_attach_chip()
1989 err = devm_request_irq(dev, info->gpmc_irq_count, in omap_nand_attach_chip()
1991 "gpmc-nand-count", info); in omap_nand_attach_chip()
1994 info->gpmc_irq_count, err); in omap_nand_attach_chip()
1995 info->gpmc_irq_count = 0; in omap_nand_attach_chip()
1999 chip->legacy.read_buf = omap_read_buf_irq_pref; in omap_nand_attach_chip()
2000 chip->legacy.write_buf = omap_write_buf_irq_pref; in omap_nand_attach_chip()
2005 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type); in omap_nand_attach_chip()
2006 return -EINVAL; in omap_nand_attach_chip()
2010 return -EINVAL; in omap_nand_attach_chip()
2016 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { in omap_nand_attach_chip()
2017 chip->ecc.mode = NAND_ECC_SOFT; in omap_nand_attach_chip()
2018 chip->ecc.algo = NAND_ECC_HAMMING; in omap_nand_attach_chip()
2022 /* Populate MTD interface based on ECC scheme */ in omap_nand_attach_chip()
2023 switch (info->ecc_opt) { in omap_nand_attach_chip()
2025 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n"); in omap_nand_attach_chip()
2026 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2027 chip->ecc.bytes = 3; in omap_nand_attach_chip()
2028 chip->ecc.size = 512; in omap_nand_attach_chip()
2029 chip->ecc.strength = 1; in omap_nand_attach_chip()
2030 chip->ecc.calculate = omap_calculate_ecc; in omap_nand_attach_chip()
2031 chip->ecc.hwctl = omap_enable_hwecc; in omap_nand_attach_chip()
2032 chip->ecc.correct = omap_correct_data; in omap_nand_attach_chip()
2034 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2036 if (!(chip->options & NAND_BUSWIDTH_16)) in omap_nand_attach_chip()
2042 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); in omap_nand_attach_chip()
2043 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2044 chip->ecc.size = 512; in omap_nand_attach_chip()
2045 chip->ecc.bytes = 7; in omap_nand_attach_chip()
2046 chip->ecc.strength = 4; in omap_nand_attach_chip()
2047 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2048 chip->ecc.correct = nand_bch_correct_data; in omap_nand_attach_chip()
2049 chip->ecc.calculate = omap_calculate_ecc_bch_sw; in omap_nand_attach_chip()
2052 oobbytes_per_step = chip->ecc.bytes + 1; in omap_nand_attach_chip()
2054 chip->ecc.priv = nand_bch_init(mtd); in omap_nand_attach_chip()
2055 if (!chip->ecc.priv) { in omap_nand_attach_chip()
2057 return -EINVAL; in omap_nand_attach_chip()
2062 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
2063 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2064 chip->ecc.size = 512; in omap_nand_attach_chip()
2065 /* 14th bit is kept reserved for ROM-code compatibility */ in omap_nand_attach_chip()
2066 chip->ecc.bytes = 7 + 1; in omap_nand_attach_chip()
2067 chip->ecc.strength = 4; in omap_nand_attach_chip()
2068 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2069 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
2070 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
2071 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
2072 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
2074 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2076 err = elm_config(info->elm_dev, BCH4_ECC, in omap_nand_attach_chip()
2077 mtd->writesize / chip->ecc.size, in omap_nand_attach_chip()
2078 chip->ecc.size, chip->ecc.bytes); in omap_nand_attach_chip()
2084 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); in omap_nand_attach_chip()
2085 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2086 chip->ecc.size = 512; in omap_nand_attach_chip()
2087 chip->ecc.bytes = 13; in omap_nand_attach_chip()
2088 chip->ecc.strength = 8; in omap_nand_attach_chip()
2089 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2090 chip->ecc.correct = nand_bch_correct_data; in omap_nand_attach_chip()
2091 chip->ecc.calculate = omap_calculate_ecc_bch_sw; in omap_nand_attach_chip()
2094 oobbytes_per_step = chip->ecc.bytes + 1; in omap_nand_attach_chip()
2096 chip->ecc.priv = nand_bch_init(mtd); in omap_nand_attach_chip()
2097 if (!chip->ecc.priv) { in omap_nand_attach_chip()
2099 return -EINVAL; in omap_nand_attach_chip()
2104 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
2105 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2106 chip->ecc.size = 512; in omap_nand_attach_chip()
2107 /* 14th bit is kept reserved for ROM-code compatibility */ in omap_nand_attach_chip()
2108 chip->ecc.bytes = 13 + 1; in omap_nand_attach_chip()
2109 chip->ecc.strength = 8; in omap_nand_attach_chip()
2110 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2111 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
2112 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
2113 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
2114 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
2116 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2118 err = elm_config(info->elm_dev, BCH8_ECC, in omap_nand_attach_chip()
2119 mtd->writesize / chip->ecc.size, in omap_nand_attach_chip()
2120 chip->ecc.size, chip->ecc.bytes); in omap_nand_attach_chip()
2127 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
2128 chip->ecc.mode = NAND_ECC_HW; in omap_nand_attach_chip()
2129 chip->ecc.size = 512; in omap_nand_attach_chip()
2130 chip->ecc.bytes = 26; in omap_nand_attach_chip()
2131 chip->ecc.strength = 16; in omap_nand_attach_chip()
2132 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2133 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
2134 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
2135 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
2136 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
2138 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2140 err = elm_config(info->elm_dev, BCH16_ECC, in omap_nand_attach_chip()
2141 mtd->writesize / chip->ecc.size, in omap_nand_attach_chip()
2142 chip->ecc.size, chip->ecc.bytes); in omap_nand_attach_chip()
2148 dev_err(dev, "Invalid or unsupported ECC scheme\n"); in omap_nand_attach_chip()
2149 return -EINVAL; in omap_nand_attach_chip()
2152 /* Check if NAND device's OOB is enough to store ECC signatures */ in omap_nand_attach_chip()
2154 (mtd->writesize / chip->ecc.size)); in omap_nand_attach_chip()
2155 if (mtd->oobsize < min_oobbytes) { in omap_nand_attach_chip()
2158 min_oobbytes, mtd->oobsize); in omap_nand_attach_chip()
2159 return -EINVAL; in omap_nand_attach_chip()
2169 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2180 struct device *dev = &pdev->dev; in omap_nand_probe()
2182 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), in omap_nand_probe()
2185 return -ENOMEM; in omap_nand_probe()
2187 info->pdev = pdev; in omap_nand_probe()
2193 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); in omap_nand_probe()
2194 if (!info->ops) { in omap_nand_probe()
2195 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n"); in omap_nand_probe()
2196 return -ENODEV; in omap_nand_probe()
2199 nand_chip = &info->nand; in omap_nand_probe()
2201 mtd->dev.parent = &pdev->dev; in omap_nand_probe()
2202 nand_chip->ecc.priv = NULL; in omap_nand_probe()
2203 nand_set_flash_node(nand_chip, dev->of_node); in omap_nand_probe()
2205 if (!mtd->name) { in omap_nand_probe()
2206 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, in omap_nand_probe()
2207 "omap2-nand.%d", info->gpmc_cs); in omap_nand_probe()
2208 if (!mtd->name) { in omap_nand_probe()
2209 dev_err(&pdev->dev, "Failed to set MTD name\n"); in omap_nand_probe()
2210 return -ENOMEM; in omap_nand_probe()
2215 nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); in omap_nand_probe()
2216 if (IS_ERR(nand_chip->legacy.IO_ADDR_R)) in omap_nand_probe()
2217 return PTR_ERR(nand_chip->legacy.IO_ADDR_R); in omap_nand_probe()
2219 info->phys_base = res->start; in omap_nand_probe()
2227 nand_chip->controller = &omap_gpmc_controller; in omap_nand_probe()
2229 nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R; in omap_nand_probe()
2230 nand_chip->legacy.cmd_ctrl = omap_hwcontrol; in omap_nand_probe()
2232 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", in omap_nand_probe()
2234 if (IS_ERR(info->ready_gpiod)) { in omap_nand_probe()
2236 return PTR_ERR(info->ready_gpiod); in omap_nand_probe()
2243 * chip delay which is slightly more than tR (AC Timing) of the NAND in omap_nand_probe()
2246 if (info->ready_gpiod) { in omap_nand_probe()
2247 nand_chip->legacy.dev_ready = omap_dev_ready; in omap_nand_probe()
2248 nand_chip->legacy.chip_delay = 0; in omap_nand_probe()
2250 nand_chip->legacy.waitfunc = omap_wait; in omap_nand_probe()
2251 nand_chip->legacy.chip_delay = 50; in omap_nand_probe()
2254 if (info->flash_bbt) in omap_nand_probe()
2255 nand_chip->bbt_options |= NAND_BBT_USE_FLASH; in omap_nand_probe()
2257 /* scan NAND device connected to chip controller */ in omap_nand_probe()
2258 nand_chip->options |= info->devsize & NAND_BUSWIDTH_16; in omap_nand_probe()
2276 if (!IS_ERR_OR_NULL(info->dma)) in omap_nand_probe()
2277 dma_release_channel(info->dma); in omap_nand_probe()
2278 if (nand_chip->ecc.priv) { in omap_nand_probe()
2279 nand_bch_free(nand_chip->ecc.priv); in omap_nand_probe()
2280 nand_chip->ecc.priv = NULL; in omap_nand_probe()
2290 if (nand_chip->ecc.priv) { in omap_nand_remove()
2291 nand_bch_free(nand_chip->ecc.priv); in omap_nand_remove()
2292 nand_chip->ecc.priv = NULL; in omap_nand_remove()
2294 if (info->dma) in omap_nand_remove()
2295 dma_release_channel(info->dma); in omap_nand_remove()
2301 { .compatible = "ti,omap2-nand", },
2319 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");