Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
34 * configurations where the chosen (data + free OOB + ECC) sizes do
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
39 * +-----------------------------------------
40 * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
41 * +-----------------------------------------
43 * -------------------------------------------
44 * ... | Data N | Free OOB bytes N | ECC N |
45 * -------------------------------------------
47 * --------------------------------------------+
48 * Last Data | Last Free OOB bytes | Last ECC |
49 * --------------------------------------------+
52 * first, then all free OOB bytes and finally all ECC bytes. With BCH,
53 * ECC bytes are 30B long and are padded with 0xFF to align on 32
58 * - It can only read 2k at a time. To overcome this limitation, the
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
62 * bits. What can be tuned is the ECC block size as long as it
64 * chip ECC requirements. For instance, using 2kiB ECC chunks
66 * - The controller will always treat data bytes, free OOB bytes
67 * and ECC bytes in that order, no matter what the real layout is
71 * - Because of these weird layouts, the Bad Block Markers can be
89 #include <linux/dma-mapping.h>
90 #include <linux/dma/pxa-dma.h>
91 #include <linux/platform_data/mtd-nand-pxa3xx.h>
111 /* System control registers/bits to enable the NAND controller on some SoCs */
122 /* NAND controller data flash control register */
141 /* NAND interface timing parameter 0 register */
155 /* NAND interface timing parameter 1 register */
164 /* NAND controller status register */
171 #define NDSR_CMDD(cs) BIT(8 - cs)
175 /* NAND ECC control register */
179 /* NAND controller data buffer register */
182 /* NAND controller command buffer 0 register */
195 /* NAND controller command buffer 1 register */
200 /* NAND controller command buffer 2 register */
205 /* NAND controller command buffer 3 register */
210 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
230 * Marvell ECC engine works differently than the others, in order to limit the
231 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
232 * per subpage, and depending on a the desired strength needed by the NAND chip,
233 * a particular layout mixing data/spare/ecc is defined, with a possible last
237 * @chunk: Desired ECC chunk size on which the layout applies
238 * @strength: Desired ECC strength (per chunk size bytes) on which the
241 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
246 * @ecc_bytes: Number of ecc bytes per chunk
249 * @last_ecc_bytes: Number of ecc bytes in the last chunk
255 int strength; member
271 .strength = ds, \
282 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
295 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
315 * NAND chip structure: stores NAND chip device related information
317 * @chip: Base NAND chip structure
318 * @node: Used to store NAND chips into a list
319 * @layout NAND layout when using hardware ECC
320 * @ndcr: Controller register value for this NAND chip
321 * @ndtr0: Timing registers 0 value for this NAND chip
322 * @ndtr1: Timing registers 1 value for this NAND chip
324 * @nsels: Number of CS lines required by the NAND chip
346 *nand) in to_nand_sel()
348 return &nand->sels[nand->selected_die]; in to_nand_sel()
352 * NAND controller capabilities for distinction between compatible strings
357 * system controller (ie. to enable the NAND controller)
375 * NAND controller structure: stores Marvell NAND controller information
379 * @regs: NAND controller registers
382 * @complete: Completion object to wait for NAND controller events
384 * @chips: List containing all the NAND chips attached to
385 * this NAND controller
386 * @caps: NAND controller capabilities for each compatible string
388 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
414 * NAND controller timings expressed in NAND Controller clock cycles
447 * @ps: Duration in pico-seconds
448 * @period_ns: Clock period in nano-seconds
450 * Convert the duration in nano-seconds, then divide by the period and
458 * NAND driver structure filled during the parsing of the ->exec_op() subop
504 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_int()
505 writel_relaxed(reg | int_mask, nfc->regs + NDCR); in marvell_nfc_disable_int()
513 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_int()
514 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); in marvell_nfc_enable_int()
521 reg = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_clear_int()
522 writel_relaxed(int_mask, nfc->regs + NDSR); in marvell_nfc_clear_int()
530 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_force_byte_access()
534 * Callers of this function do not verify if the NAND is using a 16-bit in marvell_nfc_force_byte_access()
535 * an 8-bit bus for normal operations, so we need to take care of that in marvell_nfc_force_byte_access()
536 * here by leaving the configuration unchanged if the NAND does not have in marvell_nfc_force_byte_access()
539 if (!(chip->options & NAND_BUSWIDTH_16)) in marvell_nfc_force_byte_access()
542 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_force_byte_access()
549 writel_relaxed(ndcr, nfc->regs + NDCR); in marvell_nfc_force_byte_access()
554 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_ndrun()
562 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, in marvell_nfc_wait_ndrun()
566 dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); in marvell_nfc_wait_ndrun()
567 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_wait_ndrun()
568 nfc->regs + NDCR); in marvell_nfc_wait_ndrun()
578 * - call marvell_nfc_prepare_cmd()
579 * -> activate the ND_RUN bit that will kind of 'start a job'
580 * -> wait the signal indicating the NFC is waiting for a command
581 * - send the command (cmd and address cycles)
582 * - enventually send or receive the data
583 * - call marvell_nfc_end_cmd() with the corresponding flag
584 * -> wait the flag to be triggered or cancel the job with a timeout
587 * specialized functions responsible for executing the actual NAND
592 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_prepare_cmd()
599 dev_err(nfc->dev, "Last operation did not succeed\n"); in marvell_nfc_prepare_cmd()
603 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
604 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
607 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
608 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_prepare_cmd()
612 dev_err(nfc->dev, "Timeout on WRCMDRE\n"); in marvell_nfc_prepare_cmd()
613 return -ETIMEDOUT; in marvell_nfc_prepare_cmd()
617 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
626 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_send_cmd()
628 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" in marvell_nfc_send_cmd()
630 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], in marvell_nfc_send_cmd()
631 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); in marvell_nfc_send_cmd()
633 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], in marvell_nfc_send_cmd()
634 nfc->regs + NDCB0); in marvell_nfc_send_cmd()
635 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
636 writel(nfc_op->ndcb[2], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
642 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || in marvell_nfc_send_cmd()
643 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { in marvell_nfc_send_cmd()
644 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) in marvell_nfc_send_cmd()
645 writel(nfc_op->ndcb[3], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
652 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_end_cmd()
656 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_end_cmd()
661 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", in marvell_nfc_end_cmd()
663 if (nfc->dma_chan) in marvell_nfc_end_cmd()
664 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_end_cmd()
672 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) in marvell_nfc_end_cmd()
675 writel_relaxed(flag, nfc->regs + NDSR); in marvell_nfc_end_cmd()
683 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); in marvell_nfc_wait_cmdd()
690 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_op()
698 init_completion(&nfc->complete); in marvell_nfc_wait_op()
701 ret = wait_for_completion_timeout(&nfc->complete, in marvell_nfc_wait_op()
711 dev_err(nfc->dev, "Timeout waiting for RB signal\n"); in marvell_nfc_wait_op()
712 return -ETIMEDOUT; in marvell_nfc_wait_op()
722 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_select_target()
729 ndcr_generic = readl_relaxed(nfc->regs + NDCR) & in marvell_nfc_select_target()
731 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); in marvell_nfc_select_target()
736 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) in marvell_nfc_select_target()
739 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); in marvell_nfc_select_target()
740 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
742 nfc->selected_chip = chip; in marvell_nfc_select_target()
743 marvell_nand->selected_die = die_nr; in marvell_nfc_select_target()
749 u32 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_isr()
750 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; in marvell_nfc_isr()
765 complete(&nfc->complete); in marvell_nfc_isr()
770 /* HW ECC related functions */
773 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_enable_hw_ecc()
774 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
777 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
783 if (chip->ecc.algo == NAND_ECC_BCH) in marvell_nfc_enable_hw_ecc()
784 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); in marvell_nfc_enable_hw_ecc()
790 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_disable_hw_ecc()
791 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
794 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
795 if (chip->ecc.algo == NAND_ECC_BCH) in marvell_nfc_disable_hw_ecc()
796 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_disable_hw_ecc()
805 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_dma()
806 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_enable_dma()
813 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_dma()
814 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_disable_dma()
830 sg_init_one(&sg, nfc->dma_buf, dma_len); in marvell_nfc_xfer_data_dma()
831 dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
832 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, in marvell_nfc_xfer_data_dma()
837 dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
838 return -ENXIO; in marvell_nfc_xfer_data_dma()
845 return -EIO; in marvell_nfc_xfer_data_dma()
847 dma_async_issue_pending(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
848 ret = marvell_nfc_wait_cmdd(nfc->selected_chip); in marvell_nfc_xfer_data_dma()
849 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
852 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", in marvell_nfc_xfer_data_dma()
853 dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); in marvell_nfc_xfer_data_dma()
854 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
855 return -ETIMEDOUT; in marvell_nfc_xfer_data_dma()
869 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
874 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
889 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
895 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
904 u8 *ecc, int ecc_len, in marvell_nfc_check_empty_chunk() argument
913 * check if the entire page (with ECC bytes) is actually blank or not. in marvell_nfc_check_empty_chunk()
919 if (!ecc) in marvell_nfc_check_empty_chunk()
922 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, in marvell_nfc_check_empty_chunk()
923 spare, spare_len, chip->ecc.strength); in marvell_nfc_check_empty_chunk()
925 mtd->ecc_stats.failed++; in marvell_nfc_check_empty_chunk()
930 mtd->ecc_stats.corrected += bf; in marvell_nfc_check_empty_chunk()
935 * Check a chunk is correct or not according to hardware ECC engine.
936 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
937 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
945 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_correct()
949 ndsr = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_hw_ecc_correct()
953 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_correct()
956 * Do not increment ->ecc_stats.failed now, instead, return a in marvell_nfc_hw_ecc_correct()
957 * non-zero value to indicate that this chunk was apparently in marvell_nfc_hw_ecc_correct()
959 * the chunk (with ECC bytes) is not declared empty, the calling in marvell_nfc_hw_ecc_correct()
962 return -EBADMSG; in marvell_nfc_hw_ecc_correct()
967 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_correct()
969 if (chip->ecc.algo == NAND_ECC_BCH) in marvell_nfc_hw_ecc_correct()
976 mtd->ecc_stats.corrected += bf; in marvell_nfc_hw_ecc_correct()
988 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_read_page()
989 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_read_page()
992 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_read_page()
999 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_read_page()
1003 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_read_page()
1018 * documentation, spare bytes are protected by the ECC engine, and must in marvell_nfc_hw_ecc_hmg_do_read_page()
1022 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_read_page()
1024 lt->data_bytes + oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1025 memcpy(data_buf, nfc->dma_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1026 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1028 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1039 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page_raw()
1040 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_page_raw()
1047 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_read_page()
1048 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_hmg_read_page()
1052 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page()
1054 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, in marvell_nfc_hw_ecc_hmg_read_page()
1063 * When ECC failures are detected, check if the full page has been in marvell_nfc_hw_ecc_hmg_read_page()
1068 return -ENOMEM; in marvell_nfc_hw_ecc_hmg_read_page()
1071 lt->data_bytes, true, page); in marvell_nfc_hw_ecc_hmg_read_page()
1080 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1081 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1082 * also stands for ->read_oob().
1088 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1089 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1100 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_write_page()
1101 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_write_page()
1104 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_write_page()
1111 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_write_page()
1115 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_write_page()
1129 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_write_page()
1130 memcpy(nfc->dma_buf, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1131 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1132 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + in marvell_nfc_hw_ecc_hmg_do_write_page()
1133 lt->ecc_bytes + lt->spare_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1135 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1144 PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); in marvell_nfc_hw_ecc_hmg_do_write_page()
1152 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page_raw()
1153 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page_raw()
1163 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page()
1165 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page()
1173 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1174 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1175 * also stands for ->write_oob().
1183 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1185 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1186 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1195 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page_raw()
1196 u8 *oob = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page_raw()
1197 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1198 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page_raw()
1199 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1200 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1201 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1202 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1205 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page_raw()
1208 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page_raw()
1212 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1214 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1215 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1216 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1217 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1222 buf + (lt->data_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1226 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1229 /* Read ECC bytes */ in marvell_nfc_hw_ecc_bch_read_page_raw()
1231 (ALIGN(lt->ecc_bytes, 32) * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1244 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_read_chunk()
1245 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_chunk()
1249 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_read_chunk()
1271 else if (chunk < lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_read_chunk()
1283 * Drain the FIFO, 8 32-bit reads at a time, and skip in marvell_nfc_hw_ecc_bch_read_chunk()
1310 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page()
1311 int data_len = lt->data_bytes, spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1312 u8 *data = buf, *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page()
1317 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page()
1325 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page()
1329 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1331 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page()
1332 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1333 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1353 * Please note that dumping the ECC bytes during a normal read with OOB in marvell_nfc_hw_ecc_bch_read_page()
1354 * area would add a significant overhead as ECC bytes are "consumed" by in marvell_nfc_hw_ecc_bch_read_page()
1355 * the controller in normal mode and must be re-read in raw mode. To in marvell_nfc_hw_ecc_bch_read_page()
1357 * user should re-read the page in raw mode if ECC bytes are required. in marvell_nfc_hw_ecc_bch_read_page()
1361 * In case there is any subpage read error reported by ->correct(), we in marvell_nfc_hw_ecc_bch_read_page()
1362 * usually re-read only ECC bytes in raw mode and check if the whole in marvell_nfc_hw_ecc_bch_read_page()
1363 * page is empty. In this case, it is normal that the ECC check failed in marvell_nfc_hw_ecc_bch_read_page()
1367 * 2k page, 8b strength per 512B chunk), the controller tries to correct in marvell_nfc_hw_ecc_bch_read_page()
1369 * this strange behavior, the whole page is re-read in raw mode, not in marvell_nfc_hw_ecc_bch_read_page()
1370 * only the ECC bytes. in marvell_nfc_hw_ecc_bch_read_page()
1372 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1381 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1382 lt->ecc_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1384 (chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1385 lt->last_data_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1387 (chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1388 lt->last_spare_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1390 data_off = chunk * lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1391 spare_off = chunk * lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1392 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page()
1393 lt->last_spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1394 (chunk * (lt->ecc_bytes + 2)); in marvell_nfc_hw_ecc_bch_read_page()
1396 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1397 lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1398 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1399 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1400 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1401 lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1404 * Only re-read the ECC bytes, unless we are using the 2k/8b in marvell_nfc_hw_ecc_bch_read_page()
1405 * layout which is buggy in the sense that the ECC engine will in marvell_nfc_hw_ecc_bch_read_page()
1407 * case, re-read the entire page. in marvell_nfc_hw_ecc_bch_read_page()
1409 if (lt->writesize == 2048 && lt->strength == 8) { in marvell_nfc_hw_ecc_bch_read_page()
1414 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1419 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1422 /* Check the entire chunk (data + spare + ecc) for emptyness */ in marvell_nfc_hw_ecc_bch_read_page()
1424 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1425 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1436 return chip->ecc.read_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob_raw()
1443 return chip->ecc.read_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob()
1451 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page_raw()
1452 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1453 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1454 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1455 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1457 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_write_page_raw()
1458 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1461 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page_raw()
1465 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1466 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1467 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1468 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1469 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1477 nand_write_data_op(chip, buf + (chunk * lt->data_bytes), in marvell_nfc_hw_ecc_bch_write_page_raw()
1485 nand_write_data_op(chip, chip->oob_poi + spare_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1488 /* Write the ECC bytes */ in marvell_nfc_hw_ecc_bch_write_page_raw()
1490 nand_write_data_op(chip, chip->oob_poi + ecc_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1507 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_write_chunk()
1508 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_chunk()
1525 if (lt->nchunks == 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1531 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_write_chunk()
1535 } else if (chunk < lt->nchunks - 1) { in marvell_nfc_hw_ecc_bch_write_chunk()
1542 if (chunk == lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1556 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1557 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1567 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page()
1569 const u8 *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_write_page()
1570 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1571 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1574 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page()
1578 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_write_page()
1582 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page()
1583 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page()
1584 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1585 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1594 * Waiting only for CMDD or PAGED is not enough, ECC are in marvell_nfc_hw_ecc_bch_write_page()
1603 PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); in marvell_nfc_hw_ecc_bch_write_page()
1619 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1621 return chip->ecc.write_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1629 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob()
1631 return chip->ecc.write_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob()
1634 /* NAND framework ->exec_op() hooks and related helpers */
1640 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_parse_instructions()
1648 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in marvell_nfc_parse_instructions()
1653 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1655 switch (instr->type) { in marvell_nfc_parse_instructions()
1658 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1659 NDCB0_CMD1(instr->ctx.cmd.opcode); in marvell_nfc_parse_instructions()
1661 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1662 NDCB0_CMD2(instr->ctx.cmd.opcode) | in marvell_nfc_parse_instructions()
1665 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1672 addrs = &instr->ctx.addr.addrs[offset]; in marvell_nfc_parse_instructions()
1674 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); in marvell_nfc_parse_instructions()
1677 nfc_op->ndcb[1] |= addrs[i] << (8 * i); in marvell_nfc_parse_instructions()
1680 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); in marvell_nfc_parse_instructions()
1682 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); in marvell_nfc_parse_instructions()
1684 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); in marvell_nfc_parse_instructions()
1686 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1690 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1691 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1692 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); in marvell_nfc_parse_instructions()
1693 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1694 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1698 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1700 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1704 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1705 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1706 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); in marvell_nfc_parse_instructions()
1707 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1708 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1712 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1714 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1718 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in marvell_nfc_parse_instructions()
1719 nfc_op->rdy_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1729 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_xfer_data_pio()
1730 const struct nand_op_instr *instr = nfc_op->data_instr; in marvell_nfc_xfer_data_pio()
1731 unsigned int op_id = nfc_op->data_instr_idx; in marvell_nfc_xfer_data_pio()
1734 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_xfer_data_pio()
1737 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1741 u8 *in = instr->ctx.data.buf.in + offset; in marvell_nfc_xfer_data_pio()
1745 const u8 *out = instr->ctx.data.buf.out + offset; in marvell_nfc_xfer_data_pio()
1750 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1764 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_monolithic_access_exec()
1811 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_monolithic_access_exec()
1813 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_monolithic_access_exec()
1814 nfc->regs + NDCR); in marvell_nfc_monolithic_access_exec()
1835 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1882 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
1883 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_naked_access_exec()
1885 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_naked_access_exec()
1886 nfc->regs + NDCR); in marvell_nfc_naked_access_exec()
2108 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_exec_op()
2110 marvell_nfc_select_target(chip, op->cs); in marvell_nfc_exec_op()
2112 if (nfc->caps->is_nfcv2) in marvell_nfc_exec_op()
2128 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_ecc()
2131 return -ERANGE; in marvell_nand_ooblayout_ecc()
2133 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + in marvell_nand_ooblayout_ecc()
2134 lt->last_ecc_bytes; in marvell_nand_ooblayout_ecc()
2135 oobregion->offset = mtd->oobsize - oobregion->length; in marvell_nand_ooblayout_ecc()
2144 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_free()
2147 return -ERANGE; in marvell_nand_ooblayout_free()
2153 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) in marvell_nand_ooblayout_free()
2154 oobregion->offset = 6; in marvell_nand_ooblayout_free()
2156 oobregion->offset = 2; in marvell_nand_ooblayout_free()
2158 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nand_ooblayout_free()
2159 lt->last_spare_bytes - oobregion->offset; in marvell_nand_ooblayout_free()
2165 .ecc = marvell_nand_ooblayout_ecc,
2170 struct nand_ecc_ctrl *ecc) in marvell_nand_hw_ecc_ctrl_init() argument
2173 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_hw_ecc_ctrl_init()
2177 if (!nfc->caps->is_nfcv2 && in marvell_nand_hw_ecc_ctrl_init()
2178 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { in marvell_nand_hw_ecc_ctrl_init()
2179 dev_err(nfc->dev, in marvell_nand_hw_ecc_ctrl_init()
2181 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); in marvell_nand_hw_ecc_ctrl_init()
2182 return -ENOTSUPP; in marvell_nand_hw_ecc_ctrl_init()
2185 to_marvell_nand(chip)->layout = NULL; in marvell_nand_hw_ecc_ctrl_init()
2188 if (mtd->writesize == l->writesize && in marvell_nand_hw_ecc_ctrl_init()
2189 ecc->size == l->chunk && ecc->strength == l->strength) { in marvell_nand_hw_ecc_ctrl_init()
2190 to_marvell_nand(chip)->layout = l; in marvell_nand_hw_ecc_ctrl_init()
2195 if (!to_marvell_nand(chip)->layout || in marvell_nand_hw_ecc_ctrl_init()
2196 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { in marvell_nand_hw_ecc_ctrl_init()
2197 dev_err(nfc->dev, in marvell_nand_hw_ecc_ctrl_init()
2198 "ECC strength %d at page size %d is not supported\n", in marvell_nand_hw_ecc_ctrl_init()
2199 ecc->strength, mtd->writesize); in marvell_nand_hw_ecc_ctrl_init()
2200 return -ENOTSUPP; in marvell_nand_hw_ecc_ctrl_init()
2203 /* Special care for the layout 2k/8-bit/512B */ in marvell_nand_hw_ecc_ctrl_init()
2204 if (l->writesize == 2048 && l->strength == 8) { in marvell_nand_hw_ecc_ctrl_init()
2205 if (mtd->oobsize < 128) { in marvell_nand_hw_ecc_ctrl_init()
2206 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); in marvell_nand_hw_ecc_ctrl_init()
2207 return -ENOTSUPP; in marvell_nand_hw_ecc_ctrl_init()
2209 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_hw_ecc_ctrl_init()
2214 ecc->steps = l->nchunks; in marvell_nand_hw_ecc_ctrl_init()
2215 ecc->size = l->data_bytes; in marvell_nand_hw_ecc_ctrl_init()
2217 if (ecc->strength == 1) { in marvell_nand_hw_ecc_ctrl_init()
2218 chip->ecc.algo = NAND_ECC_HAMMING; in marvell_nand_hw_ecc_ctrl_init()
2219 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; in marvell_nand_hw_ecc_ctrl_init()
2220 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; in marvell_nand_hw_ecc_ctrl_init()
2221 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2222 ecc->read_oob = ecc->read_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2223 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; in marvell_nand_hw_ecc_ctrl_init()
2224 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; in marvell_nand_hw_ecc_ctrl_init()
2225 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2226 ecc->write_oob = ecc->write_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2228 chip->ecc.algo = NAND_ECC_BCH; in marvell_nand_hw_ecc_ctrl_init()
2229 ecc->strength = 16; in marvell_nand_hw_ecc_ctrl_init()
2230 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; in marvell_nand_hw_ecc_ctrl_init()
2231 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; in marvell_nand_hw_ecc_ctrl_init()
2232 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2233 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; in marvell_nand_hw_ecc_ctrl_init()
2234 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; in marvell_nand_hw_ecc_ctrl_init()
2235 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; in marvell_nand_hw_ecc_ctrl_init()
2236 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; in marvell_nand_hw_ecc_ctrl_init()
2237 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; in marvell_nand_hw_ecc_ctrl_init()
2244 struct nand_ecc_ctrl *ecc) in marvell_nand_ecc_init() argument
2247 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_ecc_init()
2250 if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) { in marvell_nand_ecc_init()
2251 if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { in marvell_nand_ecc_init()
2252 ecc->size = chip->base.eccreq.step_size; in marvell_nand_ecc_init()
2253 ecc->strength = chip->base.eccreq.strength; in marvell_nand_ecc_init()
2255 dev_info(nfc->dev, in marvell_nand_ecc_init()
2256 "No minimum ECC strength, using 1b/512B\n"); in marvell_nand_ecc_init()
2257 ecc->size = 512; in marvell_nand_ecc_init()
2258 ecc->strength = 1; in marvell_nand_ecc_init()
2262 switch (ecc->mode) { in marvell_nand_ecc_init()
2264 ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc); in marvell_nand_ecc_init()
2271 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && in marvell_nand_ecc_init()
2272 mtd->writesize != SZ_2K) { in marvell_nand_ecc_init()
2273 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", in marvell_nand_ecc_init()
2274 mtd->writesize); in marvell_nand_ecc_init()
2275 return -EINVAL; in marvell_nand_ecc_init()
2279 return -EINVAL; in marvell_nand_ecc_init()
2313 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_setup_data_interface()
2314 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; in marvell_nfc_setup_data_interface()
2324 * SDR timings are given in pico-seconds while NFC timings must be in marvell_nfc_setup_data_interface()
2325 * expressed in NAND controller clock cycles, which is half of the in marvell_nfc_setup_data_interface()
2326 * frequency of the accessible ECC clock retrieved by clk_get_rate(). in marvell_nfc_setup_data_interface()
2334 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; in marvell_nfc_setup_data_interface()
2336 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; in marvell_nfc_setup_data_interface()
2338 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); in marvell_nfc_setup_data_interface()
2339 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; in marvell_nfc_setup_data_interface()
2340 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); in marvell_nfc_setup_data_interface()
2343 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In in marvell_nfc_setup_data_interface()
2347 read_delay = sdr->tRC_min >= 30000 ? in marvell_nfc_setup_data_interface()
2350 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); in marvell_nfc_setup_data_interface()
2356 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_data_interface()
2357 period_ns) - 2, in marvell_nfc_setup_data_interface()
2358 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_data_interface()
2365 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_data_interface()
2366 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_data_interface()
2368 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_data_interface()
2371 nfc_tmg.tR = nfc_tmg.tCH - 3; in marvell_nfc_setup_data_interface()
2379 marvell_nand->ndtr0 = in marvell_nfc_setup_data_interface()
2388 marvell_nand->ndtr1 = in marvell_nfc_setup_data_interface()
2393 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_data_interface()
2394 marvell_nand->ndtr0 |= in marvell_nfc_setup_data_interface()
2399 marvell_nand->ndtr1 |= in marvell_nfc_setup_data_interface()
2411 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_attach_chip()
2412 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); in marvell_nand_attach_chip()
2415 if (pdata && pdata->flash_bbt) in marvell_nand_attach_chip()
2416 chip->bbt_options |= NAND_BBT_USE_FLASH; in marvell_nand_attach_chip()
2418 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in marvell_nand_attach_chip()
2420 * We'll use a bad block table stored in-flash and don't in marvell_nand_attach_chip()
2423 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_attach_chip()
2424 chip->bbt_td = &bbt_main_descr; in marvell_nand_attach_chip()
2425 chip->bbt_md = &bbt_mirror_descr; in marvell_nand_attach_chip()
2428 /* Save the chip-specific fields of NDCR */ in marvell_nand_attach_chip()
2429 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); in marvell_nand_attach_chip()
2430 if (chip->options & NAND_BUSWIDTH_16) in marvell_nand_attach_chip()
2431 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; in marvell_nand_attach_chip()
2437 if (mtd->writesize <= 512) { in marvell_nand_attach_chip()
2438 marvell_nand->addr_cyc = 1; in marvell_nand_attach_chip()
2440 marvell_nand->addr_cyc = 2; in marvell_nand_attach_chip()
2441 marvell_nand->ndcr |= NDCR_RA_START; in marvell_nand_attach_chip()
2452 if (chip->options & NAND_ROW_ADDR_3) in marvell_nand_attach_chip()
2453 marvell_nand->addr_cyc += 3; in marvell_nand_attach_chip()
2455 marvell_nand->addr_cyc += 2; in marvell_nand_attach_chip()
2458 chip->ecc.size = pdata->ecc_step_size; in marvell_nand_attach_chip()
2459 chip->ecc.strength = pdata->ecc_strength; in marvell_nand_attach_chip()
2462 ret = marvell_nand_ecc_init(mtd, &chip->ecc); in marvell_nand_attach_chip()
2464 dev_err(nfc->dev, "ECC init failed: %d\n", ret); in marvell_nand_attach_chip()
2468 if (chip->ecc.mode == NAND_ECC_HW) { in marvell_nand_attach_chip()
2470 * Subpage write not available with hardware ECC, prohibit also in marvell_nand_attach_chip()
2473 * uncorrectable ECC errors. in marvell_nand_attach_chip()
2475 chip->options |= NAND_NO_SUBPAGE_WRITE; in marvell_nand_attach_chip()
2478 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_attach_chip()
2484 mtd->name = "pxa3xx_nand-0"; in marvell_nand_attach_chip()
2485 } else if (!mtd->name) { in marvell_nand_attach_chip()
2489 * should define the following property in your NAND node, ie: in marvell_nand_attach_chip()
2491 * label = "main-storage"; in marvell_nand_attach_chip()
2493 * This way, mtd->name will be set by the core when in marvell_nand_attach_chip()
2496 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, in marvell_nand_attach_chip()
2497 "%s:nand.%d", dev_name(nfc->dev), in marvell_nand_attach_chip()
2498 marvell_nand->sels[0].cs); in marvell_nand_attach_chip()
2499 if (!mtd->name) { in marvell_nand_attach_chip()
2500 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); in marvell_nand_attach_chip()
2501 return -ENOMEM; in marvell_nand_attach_chip()
2525 * The legacy "num-cs" property indicates the number of CS on the only in marvell_nand_chip_init()
2529 * When not using legacy bindings, a couple of "reg" and "nand-rb" in marvell_nand_chip_init()
2531 * "reg" points to the CS lines and "nand-rb" to the RB line. in marvell_nand_chip_init()
2533 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2539 return -EINVAL; in marvell_nand_chip_init()
2543 /* Alloc the nand chip structure */ in marvell_nand_chip_init()
2549 return -ENOMEM; in marvell_nand_chip_init()
2552 marvell_nand->nsels = nsels; in marvell_nand_chip_init()
2553 marvell_nand->selected_die = -1; in marvell_nand_chip_init()
2556 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2572 if (cs >= nfc->caps->max_cs_nb) { in marvell_nand_chip_init()
2574 cs, nfc->caps->max_cs_nb); in marvell_nand_chip_init()
2575 return -EINVAL; in marvell_nand_chip_init()
2578 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in marvell_nand_chip_init()
2580 return -EINVAL; in marvell_nand_chip_init()
2591 marvell_nand->sels[i].cs = cs; in marvell_nand_chip_init()
2595 marvell_nand->sels[i].ndcb0_csel = 0; in marvell_nand_chip_init()
2599 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; in marvell_nand_chip_init()
2602 return -EINVAL; in marvell_nand_chip_init()
2606 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2610 ret = of_property_read_u32_index(np, "nand-rb", i, in marvell_nand_chip_init()
2620 if (rb >= nfc->caps->max_rb_nb) { in marvell_nand_chip_init()
2622 rb, nfc->caps->max_rb_nb); in marvell_nand_chip_init()
2623 return -EINVAL; in marvell_nand_chip_init()
2626 marvell_nand->sels[i].rb = rb; in marvell_nand_chip_init()
2629 chip = &marvell_nand->chip; in marvell_nand_chip_init()
2630 chip->controller = &nfc->controller; in marvell_nand_chip_init()
2633 if (!of_property_read_bool(np, "marvell,nand-keep-config")) in marvell_nand_chip_init()
2634 chip->options |= NAND_KEEP_TIMINGS; in marvell_nand_chip_init()
2637 mtd->dev.parent = dev; in marvell_nand_chip_init()
2640 * Default to HW ECC engine mode. If the nand-ecc-mode property is given in marvell_nand_chip_init()
2643 chip->ecc.mode = NAND_ECC_HW; in marvell_nand_chip_init()
2647 * ->setup_data_interface() is called. in marvell_nand_chip_init()
2649 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); in marvell_nand_chip_init()
2650 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
2652 chip->options |= NAND_BUSWIDTH_AUTO; in marvell_nand_chip_init()
2654 ret = nand_scan(chip, marvell_nand->nsels); in marvell_nand_chip_init()
2656 dev_err(dev, "could not scan the nand chip\n"); in marvell_nand_chip_init()
2662 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); in marvell_nand_chip_init()
2671 list_add_tail(&marvell_nand->node, &nfc->chips); in marvell_nand_chip_init()
2678 struct device_node *np = dev->of_node; in marvell_nand_chips_init()
2680 int max_cs = nfc->caps->max_cs_nb; in marvell_nand_chips_init()
2690 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, in marvell_nand_chips_init()
2692 return -EINVAL; in marvell_nand_chips_init()
2696 * Legacy bindings do not use child nodes to exhibit NAND chip in marvell_nand_chips_init()
2697 * properties and layout. Instead, NAND properties are mixed with the in marvell_nand_chips_init()
2699 * NAND controller node. in marvell_nand_chips_init()
2701 if (nfc->caps->legacy_of_bindings) { in marvell_nand_chips_init()
2721 list_for_each_entry_safe(entry, temp, &nfc->chips, node) { in marvell_nand_chips_cleanup()
2722 nand_release(&entry->chip); in marvell_nand_chips_cleanup()
2723 list_del(&entry->node); in marvell_nand_chips_cleanup()
2729 struct platform_device *pdev = container_of(nfc->dev, in marvell_nfc_init_dma()
2737 dev_warn(nfc->dev, in marvell_nfc_init_dma()
2739 return -ENOTSUPP; in marvell_nfc_init_dma()
2742 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); in marvell_nfc_init_dma()
2746 nfc->dma_chan = dma_request_slave_channel(nfc->dev, "data"); in marvell_nfc_init_dma()
2747 if (!nfc->dma_chan) { in marvell_nfc_init_dma()
2748 dev_err(nfc->dev, in marvell_nfc_init_dma()
2750 return -ENODEV; in marvell_nfc_init_dma()
2755 return -ENXIO; in marvell_nfc_init_dma()
2759 config.src_addr = r->start + NDDB; in marvell_nfc_init_dma()
2760 config.dst_addr = r->start + NDDB; in marvell_nfc_init_dma()
2763 ret = dmaengine_slave_config(nfc->dma_chan, &config); in marvell_nfc_init_dma()
2765 dev_err(nfc->dev, "Failed to configure DMA channel\n"); in marvell_nfc_init_dma()
2775 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); in marvell_nfc_init_dma()
2776 if (!nfc->dma_buf) in marvell_nfc_init_dma()
2777 return -ENOMEM; in marvell_nfc_init_dma()
2779 nfc->use_dma = true; in marvell_nfc_init_dma()
2787 * ECC operations and interruptions are only enabled when specifically in marvell_nfc_reset()
2788 * needed. ECC shall not be activated in the early stages (fails probe). in marvell_nfc_reset()
2790 * SPARE_EN bit must always be set or ECC bytes will not be at the same in marvell_nfc_reset()
2794 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); in marvell_nfc_reset()
2795 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); in marvell_nfc_reset()
2796 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_reset()
2801 struct device_node *np = nfc->dev->of_node; in marvell_nfc_init()
2804 * Some SoCs like A7k/A8k need to enable manually the NAND in marvell_nfc_init()
2809 if (nfc->caps->need_system_controller) { in marvell_nfc_init()
2812 "marvell,system-controller"); in marvell_nfc_init()
2833 if (!nfc->caps->is_nfcv2) in marvell_nfc_init()
2843 struct device *dev = &pdev->dev; in marvell_nfc_probe()
2849 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), in marvell_nfc_probe()
2852 return -ENOMEM; in marvell_nfc_probe()
2854 nfc->dev = dev; in marvell_nfc_probe()
2855 nand_controller_init(&nfc->controller); in marvell_nfc_probe()
2856 nfc->controller.ops = &marvell_nand_controller_ops; in marvell_nfc_probe()
2857 INIT_LIST_HEAD(&nfc->chips); in marvell_nfc_probe()
2860 nfc->regs = devm_ioremap_resource(dev, r); in marvell_nfc_probe()
2861 if (IS_ERR(nfc->regs)) in marvell_nfc_probe()
2862 return PTR_ERR(nfc->regs); in marvell_nfc_probe()
2870 nfc->core_clk = devm_clk_get(&pdev->dev, "core"); in marvell_nfc_probe()
2873 if (nfc->core_clk == ERR_PTR(-ENOENT)) in marvell_nfc_probe()
2874 nfc->core_clk = devm_clk_get(&pdev->dev, NULL); in marvell_nfc_probe()
2876 if (IS_ERR(nfc->core_clk)) in marvell_nfc_probe()
2877 return PTR_ERR(nfc->core_clk); in marvell_nfc_probe()
2879 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_probe()
2883 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); in marvell_nfc_probe()
2884 if (IS_ERR(nfc->reg_clk)) { in marvell_nfc_probe()
2885 if (PTR_ERR(nfc->reg_clk) != -ENOENT) { in marvell_nfc_probe()
2886 ret = PTR_ERR(nfc->reg_clk); in marvell_nfc_probe()
2890 nfc->reg_clk = NULL; in marvell_nfc_probe()
2893 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_probe()
2900 0, "marvell-nfc", nfc); in marvell_nfc_probe()
2904 /* Get NAND controller capabilities */ in marvell_nfc_probe()
2905 if (pdev->id_entry) in marvell_nfc_probe()
2906 nfc->caps = (void *)pdev->id_entry->driver_data; in marvell_nfc_probe()
2908 nfc->caps = of_device_get_match_data(&pdev->dev); in marvell_nfc_probe()
2910 if (!nfc->caps) { in marvell_nfc_probe()
2912 ret = -EINVAL; in marvell_nfc_probe()
2930 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_probe()
2932 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_probe()
2943 if (nfc->use_dma) { in marvell_nfc_remove()
2944 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_remove()
2945 dma_release_channel(nfc->dma_chan); in marvell_nfc_remove()
2948 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_remove()
2949 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_remove()
2959 list_for_each_entry(chip, &nfc->chips, node) in marvell_nfc_suspend()
2960 marvell_nfc_wait_ndrun(&chip->chip); in marvell_nfc_suspend()
2962 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_suspend()
2963 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_suspend()
2973 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_resume()
2977 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_resume()
2982 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_resume()
2985 nfc->selected_chip = NULL; in marvell_nfc_resume()
3040 .name = "pxa3xx-nand",
3049 .compatible = "marvell,armada-8k-nand-controller",
3053 .compatible = "marvell,armada370-nand-controller",
3057 .compatible = "marvell,pxa3xx-nand-controller",
3062 .compatible = "marvell,armada-8k-nand",
3066 .compatible = "marvell,armada370-nand",
3070 .compatible = "marvell,pxa3xx-nand",
3079 .name = "marvell-nfc",
3090 MODULE_DESCRIPTION("Marvell NAND controller driver");