1 // SPDX-License-Identifier: GPL-2.0-only
9  *   This is a device driver for the NAND flash controller found on
11  *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12  *   where 0-3 reflects the chip select for NAND.
34 /* NAND Timing MSRs */
35 #define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */
39 /* NAND BAR MSRs */
46 #define FLSH_NOR_NAND		(1ULL<<33)	/* 1 for NAND */
55 /* Registers within the NAND flash controller BAR -- memory mapped */
57 #define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
58 #define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
66 /* Registers within the NAND flash controller BAR -- I/O mapped */
77 #define CS_NAND_CTL_DIST_EN	(1<<4)	/* Enable NAND Distract interrupt */
95 		memcpy_fromio(buf, this->legacy.IO_ADDR_R, 0x800);  in cs553x_read_buf()
97 		len -= 0x800;  in cs553x_read_buf()
99 	memcpy_fromio(buf, this->legacy.IO_ADDR_R, len);  in cs553x_read_buf()
105 		memcpy_toio(this->legacy.IO_ADDR_R, buf, 0x800);  in cs553x_write_buf()
107 		len -= 0x800;  in cs553x_write_buf()
109 	memcpy_toio(this->legacy.IO_ADDR_R, buf, len);  in cs553x_write_buf()
114 	return readb(this->legacy.IO_ADDR_R);  in cs553x_read_byte()
121 	while (i && readb(this->legacy.IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {  in cs553x_write_byte()
123 		i--;  in cs553x_write_byte()
125 	writeb(byte, this->legacy.IO_ADDR_W + 0x801);  in cs553x_write_byte()
131 	void __iomem *mmio_base = this->legacy.IO_ADDR_R;  in cs553x_hwcontrol()
142 	void __iomem *mmio_base = this->legacy.IO_ADDR_R;  in cs553x_device_ready()
148 static void cs_enable_hwecc(struct nand_chip *this, int mode)  in cs_enable_hwecc()  argument
150 	void __iomem *mmio_base = this->legacy.IO_ADDR_R;  in cs_enable_hwecc()
158 	uint32_t ecc;  in cs_calculate_ecc()  local
159 	void __iomem *mmio_base = this->legacy.IO_ADDR_R;  in cs_calculate_ecc()
161 	ecc = readl(mmio_base + MM_NAND_STS);  in cs_calculate_ecc()
163 	ecc_code[1] = ecc >> 8;  in cs_calculate_ecc()
164 	ecc_code[0] = ecc >> 16;  in cs_calculate_ecc()
165 	ecc_code[2] = ecc >> 24;  in cs_calculate_ecc()
177 	pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",  in cs553x_init_one()
181 		pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");  in cs553x_init_one()
182 		return -ENXIO;  in cs553x_init_one()
188 		err = -ENOMEM;  in cs553x_init_one()
195 	new_mtd->owner = THIS_MODULE;  in cs553x_init_one()
198 	this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = ioremap(adr, 4096);  in cs553x_init_one()
199 	if (!this->legacy.IO_ADDR_R) {  in cs553x_init_one()
200 		pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);  in cs553x_init_one()
201 		err = -EIO;  in cs553x_init_one()
205 	this->legacy.cmd_ctrl = cs553x_hwcontrol;  in cs553x_init_one()
206 	this->legacy.dev_ready = cs553x_device_ready;  in cs553x_init_one()
207 	this->legacy.read_byte = cs553x_read_byte;  in cs553x_init_one()
208 	this->legacy.read_buf = cs553x_read_buf;  in cs553x_init_one()
209 	this->legacy.write_buf = cs553x_write_buf;  in cs553x_init_one()
211 	this->legacy.chip_delay = 0;  in cs553x_init_one()
213 	this->ecc.mode = NAND_ECC_HW;  in cs553x_init_one()
214 	this->ecc.size = 256;  in cs553x_init_one()
215 	this->ecc.bytes = 3;  in cs553x_init_one()
216 	this->ecc.hwctl  = cs_enable_hwecc;  in cs553x_init_one()
217 	this->ecc.calculate = cs_calculate_ecc;  in cs553x_init_one()
218 	this->ecc.correct  = nand_correct_data;  in cs553x_init_one()
219 	this->ecc.strength = 1;  in cs553x_init_one()
222 	this->bbt_options = NAND_BBT_USE_FLASH;  in cs553x_init_one()
224 	new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);  in cs553x_init_one()
225 	if (!new_mtd->name) {  in cs553x_init_one()
226 		err = -ENOMEM;  in cs553x_init_one()
239 	kfree(new_mtd->name);  in cs553x_init_one()
241 	iounmap(this->legacy.IO_ADDR_R);  in cs553x_init_one()
267 	int err = -ENXIO;  in cs553x_init()
273 		return -ENXIO;  in cs553x_init()
279 		return -ENXIO;  in cs553x_init()
281 	/* If it doesn't have the NAND controller enabled, abort */  in cs553x_init()
284 		pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");  in cs553x_init()
285 		return -ENXIO;  in cs553x_init()
323 		mmio_base = this->legacy.IO_ADDR_R;  in cs553x_cleanup()
327 		kfree(mtd->name);  in cs553x_cleanup()
342 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");