Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
65 #include <soc/at91/atmel-sfr.h>
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
201 struct atmel_nand *nand);
203 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
277 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; in atmel_nfc_op_done()
278 op->wait ^= status & op->wait; in atmel_nfc_op_done()
280 return !op->wait || op->errors; in atmel_nfc_op_done()
289 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); in atmel_nfc_interrupt()
291 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_interrupt()
292 done = atmel_nfc_op_done(&nc->op, sr); in atmel_nfc_interrupt()
295 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); in atmel_nfc_interrupt()
298 complete(&nc->complete); in atmel_nfc_interrupt()
314 ret = regmap_read_poll_timeout(nc->base.smc, in atmel_nfc_wait()
316 atmel_nfc_op_done(&nc->op, in atmel_nfc_wait()
320 init_completion(&nc->complete); in atmel_nfc_wait()
321 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, in atmel_nfc_wait()
322 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_wait()
323 ret = wait_for_completion_timeout(&nc->complete, in atmel_nfc_wait()
326 ret = -ETIMEDOUT; in atmel_nfc_wait()
330 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_nfc_wait()
333 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { in atmel_nfc_wait()
334 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
335 ret = -ETIMEDOUT; in atmel_nfc_wait()
338 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { in atmel_nfc_wait()
339 dev_err(nc->base.dev, "Access to an undefined area\n"); in atmel_nfc_wait()
340 ret = -EIO; in atmel_nfc_wait()
343 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { in atmel_nfc_wait()
344 dev_err(nc->base.dev, "Access while busy\n"); in atmel_nfc_wait()
345 ret = -EIO; in atmel_nfc_wait()
348 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { in atmel_nfc_wait()
349 dev_err(nc->base.dev, "Wrong access size\n"); in atmel_nfc_wait()
350 ret = -EIO; in atmel_nfc_wait()
372 buf_dma = dma_map_single(nc->dev, buf, len, dir); in atmel_nand_dma_transfer()
373 if (dma_mapping_error(nc->dev, dev_dma)) { in atmel_nand_dma_transfer()
374 dev_err(nc->dev, in atmel_nand_dma_transfer()
387 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len, in atmel_nand_dma_transfer()
390 dev_err(nc->dev, "Failed to prepare DMA memcpy\n"); in atmel_nand_dma_transfer()
394 tx->callback = atmel_nand_dma_transfer_finished; in atmel_nand_dma_transfer()
395 tx->callback_param = &finished; in atmel_nand_dma_transfer()
399 dev_err(nc->dev, "Failed to do DMA tx_submit\n"); in atmel_nand_dma_transfer()
403 dma_async_issue_pending(nc->dmac); in atmel_nand_dma_transfer()
409 dma_unmap_single(nc->dev, buf_dma, len, dir); in atmel_nand_dma_transfer()
412 dev_dbg(nc->dev, "Fall back to CPU I/O\n"); in atmel_nand_dma_transfer()
414 return -EIO; in atmel_nand_dma_transfer()
419 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_byte() local
421 return ioread8(nand->activecs->io.virt); in atmel_nand_read_byte()
426 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_write_byte() local
428 if (chip->options & NAND_BUSWIDTH_16) in atmel_nand_write_byte()
429 iowrite16(byte | (byte << 8), nand->activecs->io.virt); in atmel_nand_write_byte()
431 iowrite8(byte, nand->activecs->io.virt); in atmel_nand_write_byte()
436 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_buf() local
439 nc = to_nand_controller(chip->controller); in atmel_nand_read_buf()
442 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_read_buf()
444 * a DMA transfer. If it fails, fallback to PIO mode. in atmel_nand_read_buf()
446 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_read_buf()
448 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, in atmel_nand_read_buf()
452 if (chip->options & NAND_BUSWIDTH_16) in atmel_nand_read_buf()
453 ioread16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_read_buf()
455 ioread8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_read_buf()
460 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_write_buf() local
463 nc = to_nand_controller(chip->controller); in atmel_nand_write_buf()
466 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_write_buf()
468 * a DMA transfer. If it fails, fallback to PIO mode. in atmel_nand_write_buf()
470 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_write_buf()
472 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, in atmel_nand_write_buf()
476 if (chip->options & NAND_BUSWIDTH_16) in atmel_nand_write_buf()
477 iowrite16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_write_buf()
479 iowrite8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_write_buf()
484 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_dev_ready() local
486 return gpiod_get_value(nand->activecs->rb.gpio); in atmel_nand_dev_ready()
491 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_select_chip() local
493 if (cs < 0 || cs >= nand->numcs) { in atmel_nand_select_chip()
494 nand->activecs = NULL; in atmel_nand_select_chip()
495 chip->legacy.dev_ready = NULL; in atmel_nand_select_chip()
499 nand->activecs = &nand->cs[cs]; in atmel_nand_select_chip()
501 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB) in atmel_nand_select_chip()
502 chip->legacy.dev_ready = atmel_nand_dev_ready; in atmel_nand_select_chip()
507 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_dev_ready() local
511 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_dev_ready()
513 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status); in atmel_hsmc_nand_dev_ready()
515 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); in atmel_hsmc_nand_dev_ready()
521 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_select_chip() local
524 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_select_chip()
528 if (!nand->activecs) { in atmel_hsmc_nand_select_chip()
529 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_select_chip()
534 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_select_chip()
535 chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready; in atmel_hsmc_nand_select_chip()
537 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_select_chip()
542 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | in atmel_hsmc_nand_select_chip()
543 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | in atmel_hsmc_nand_select_chip()
545 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_select_chip()
551 u8 *addrs = nc->op.addrs; in atmel_nfc_exec_op()
556 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; in atmel_nfc_exec_op()
558 for (i = 0; i < nc->op.ncmds; i++) in atmel_nfc_exec_op()
559 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); in atmel_nfc_exec_op()
561 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) in atmel_nfc_exec_op()
562 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); in atmel_nfc_exec_op()
564 op |= ATMEL_NFC_CSID(nc->op.cs) | in atmel_nfc_exec_op()
565 ATMEL_NFC_ACYCLE(nc->op.naddrs); in atmel_nfc_exec_op()
567 if (nc->op.ncmds > 1) in atmel_nfc_exec_op()
573 if (nc->op.data != ATMEL_NFC_NO_DATA) { in atmel_nfc_exec_op()
575 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; in atmel_nfc_exec_op()
577 if (nc->op.data == ATMEL_NFC_WRITE_DATA) in atmel_nfc_exec_op()
582 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); in atmel_nfc_exec_op()
585 regmap_write(nc->io, op, addr); in atmel_nfc_exec_op()
589 dev_err(nc->base.dev, in atmel_nfc_exec_op()
590 "Failed to send NAND command (err = %d)!", in atmel_nfc_exec_op()
594 memset(&nc->op, 0, sizeof(nc->op)); in atmel_nfc_exec_op()
602 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_cmd_ctrl() local
605 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_cmd_ctrl()
608 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) in atmel_hsmc_nand_cmd_ctrl()
611 nc->op.addrs[nc->op.naddrs++] = dat; in atmel_hsmc_nand_cmd_ctrl()
613 if (nc->op.ncmds > 1) in atmel_hsmc_nand_cmd_ctrl()
616 nc->op.cmds[nc->op.ncmds++] = dat; in atmel_hsmc_nand_cmd_ctrl()
620 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_cmd_ctrl()
628 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_cmd_ctrl() local
631 nc = to_nand_controller(chip->controller); in atmel_nand_cmd_ctrl()
633 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) { in atmel_nand_cmd_ctrl()
635 gpiod_set_value(nand->activecs->csgpio, 0); in atmel_nand_cmd_ctrl()
637 gpiod_set_value(nand->activecs->csgpio, 1); in atmel_nand_cmd_ctrl()
641 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs); in atmel_nand_cmd_ctrl()
643 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs); in atmel_nand_cmd_ctrl()
651 int ret = -EIO; in atmel_nfc_copy_to_sram()
653 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_to_sram()
655 if (nc->base.dmac) in atmel_nfc_copy_to_sram()
656 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, in atmel_nfc_copy_to_sram()
657 nc->sram.dma, mtd->writesize, in atmel_nfc_copy_to_sram()
662 memcpy_toio(nc->sram.virt, buf, mtd->writesize); in atmel_nfc_copy_to_sram()
665 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, in atmel_nfc_copy_to_sram()
666 mtd->oobsize); in atmel_nfc_copy_to_sram()
674 int ret = -EIO; in atmel_nfc_copy_from_sram()
676 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_from_sram()
678 if (nc->base.dmac) in atmel_nfc_copy_from_sram()
679 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, in atmel_nfc_copy_from_sram()
680 mtd->writesize, DMA_FROM_DEVICE); in atmel_nfc_copy_from_sram()
684 memcpy_fromio(buf, nc->sram.virt, mtd->writesize); in atmel_nfc_copy_from_sram()
687 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, in atmel_nfc_copy_from_sram()
688 mtd->oobsize); in atmel_nfc_copy_from_sram()
696 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_set_op_addr()
699 nc->op.addrs[nc->op.naddrs++] = column; in atmel_nfc_set_op_addr()
704 if (mtd->writesize > 512) in atmel_nfc_set_op_addr()
705 nc->op.addrs[nc->op.naddrs++] = column >> 8; in atmel_nfc_set_op_addr()
709 nc->op.addrs[nc->op.naddrs++] = page; in atmel_nfc_set_op_addr()
710 nc->op.addrs[nc->op.naddrs++] = page >> 8; in atmel_nfc_set_op_addr()
712 if (chip->options & NAND_ROW_ADDR_3) in atmel_nfc_set_op_addr()
713 nc->op.addrs[nc->op.naddrs++] = page >> 16; in atmel_nfc_set_op_addr()
719 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_enable() local
723 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_enable()
728 ret = atmel_pmecc_enable(nand->pmecc, op); in atmel_nand_pmecc_enable()
730 dev_err(nc->dev, in atmel_nand_pmecc_enable()
731 "Failed to enable ECC engine (err = %d)\n", ret); in atmel_nand_pmecc_enable()
738 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_disable() local
741 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_disable()
746 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_generate_eccbytes() local
753 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_generate_eccbytes()
758 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_generate_eccbytes()
760 dev_err(nc->dev, in atmel_nand_pmecc_generate_eccbytes()
761 "Failed to transfer NAND page data (err = %d)\n", in atmel_nand_pmecc_generate_eccbytes()
767 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_generate_eccbytes()
769 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_generate_eccbytes()
770 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, in atmel_nand_pmecc_generate_eccbytes()
772 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_generate_eccbytes()
781 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_correct_data() local
788 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_correct_data()
793 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_correct_data()
795 dev_err(nc->dev, in atmel_nand_pmecc_correct_data()
796 "Failed to read NAND page data (err = %d)\n", in atmel_nand_pmecc_correct_data()
802 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_correct_data()
805 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_correct_data()
806 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, in atmel_nand_pmecc_correct_data()
808 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) in atmel_nand_pmecc_correct_data()
810 chip->ecc.size, in atmel_nand_pmecc_correct_data()
812 chip->ecc.bytes, in atmel_nand_pmecc_correct_data()
814 chip->ecc.strength); in atmel_nand_pmecc_correct_data()
819 mtd->ecc_stats.failed++; in atmel_nand_pmecc_correct_data()
821 databuf += chip->ecc.size; in atmel_nand_pmecc_correct_data()
822 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_correct_data()
832 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_write_pg() local
841 atmel_nand_write_buf(chip, buf, mtd->writesize); in atmel_nand_pmecc_write_pg()
845 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_write_pg()
851 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize); in atmel_nand_pmecc_write_pg()
881 atmel_nand_read_buf(chip, buf, mtd->writesize); in atmel_nand_pmecc_read_pg()
882 atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize); in atmel_nand_pmecc_read_pg()
908 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_write_pg() local
912 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_write_pg()
916 nc->op.cmds[0] = NAND_CMD_SEQIN; in atmel_hsmc_nand_pmecc_write_pg()
917 nc->op.ncmds = 1; in atmel_hsmc_nand_pmecc_write_pg()
919 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_write_pg()
920 nc->op.data = ATMEL_NFC_WRITE_DATA; in atmel_hsmc_nand_pmecc_write_pg()
929 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_write_pg()
930 "Failed to transfer NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_write_pg()
942 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize); in atmel_hsmc_nand_pmecc_write_pg()
944 nc->op.cmds[0] = NAND_CMD_PAGEPROG; in atmel_hsmc_nand_pmecc_write_pg()
945 nc->op.ncmds = 1; in atmel_hsmc_nand_pmecc_write_pg()
946 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_write_pg()
949 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n", in atmel_hsmc_nand_pmecc_write_pg()
952 status = chip->legacy.waitfunc(chip); in atmel_hsmc_nand_pmecc_write_pg()
954 return -EIO; in atmel_hsmc_nand_pmecc_write_pg()
980 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_read_pg() local
984 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_read_pg()
987 * Optimized read page accessors only work when the NAND R/B pin is in atmel_hsmc_nand_pmecc_read_pg()
989 * to the non-optimized one. in atmel_hsmc_nand_pmecc_read_pg()
991 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) { in atmel_hsmc_nand_pmecc_read_pg()
998 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; in atmel_hsmc_nand_pmecc_read_pg()
1000 if (mtd->writesize > 512) in atmel_hsmc_nand_pmecc_read_pg()
1001 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; in atmel_hsmc_nand_pmecc_read_pg()
1004 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_read_pg()
1005 nc->op.data = ATMEL_NFC_READ_DATA; in atmel_hsmc_nand_pmecc_read_pg()
1014 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_read_pg()
1015 "Failed to load NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_read_pg()
1047 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_init() local
1051 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_init()
1053 if (!nc->pmecc) { in atmel_nand_pmecc_init()
1054 dev_err(nc->dev, "HW ECC not supported\n"); in atmel_nand_pmecc_init()
1055 return -ENOTSUPP; in atmel_nand_pmecc_init()
1058 if (nc->caps->legacy_of_bindings) { in atmel_nand_pmecc_init()
1061 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap", in atmel_nand_pmecc_init()
1063 chip->ecc.strength = val; in atmel_nand_pmecc_init()
1065 if (!of_property_read_u32(nc->dev->of_node, in atmel_nand_pmecc_init()
1066 "atmel,pmecc-sector-size", in atmel_nand_pmecc_init()
1068 chip->ecc.size = val; in atmel_nand_pmecc_init()
1071 if (chip->ecc.options & NAND_ECC_MAXIMIZE) in atmel_nand_pmecc_init()
1072 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; in atmel_nand_pmecc_init()
1073 else if (chip->ecc.strength) in atmel_nand_pmecc_init()
1074 req.ecc.strength = chip->ecc.strength; in atmel_nand_pmecc_init()
1075 else if (chip->base.eccreq.strength) in atmel_nand_pmecc_init()
1076 req.ecc.strength = chip->base.eccreq.strength; in atmel_nand_pmecc_init()
1078 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; in atmel_nand_pmecc_init()
1080 if (chip->ecc.size) in atmel_nand_pmecc_init()
1081 req.ecc.sectorsize = chip->ecc.size; in atmel_nand_pmecc_init()
1082 else if (chip->base.eccreq.step_size) in atmel_nand_pmecc_init()
1083 req.ecc.sectorsize = chip->base.eccreq.step_size; in atmel_nand_pmecc_init()
1085 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; in atmel_nand_pmecc_init()
1087 req.pagesize = mtd->writesize; in atmel_nand_pmecc_init()
1088 req.oobsize = mtd->oobsize; in atmel_nand_pmecc_init()
1090 if (mtd->writesize <= 512) { in atmel_nand_pmecc_init()
1091 req.ecc.bytes = 4; in atmel_nand_pmecc_init()
1092 req.ecc.ooboffset = 0; in atmel_nand_pmecc_init()
1094 req.ecc.bytes = mtd->oobsize - 2; in atmel_nand_pmecc_init()
1095 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO; in atmel_nand_pmecc_init()
1098 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); in atmel_nand_pmecc_init()
1099 if (IS_ERR(nand->pmecc)) in atmel_nand_pmecc_init()
1100 return PTR_ERR(nand->pmecc); in atmel_nand_pmecc_init()
1102 chip->ecc.algo = NAND_ECC_BCH; in atmel_nand_pmecc_init()
1103 chip->ecc.size = req.ecc.sectorsize; in atmel_nand_pmecc_init()
1104 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; in atmel_nand_pmecc_init()
1105 chip->ecc.strength = req.ecc.strength; in atmel_nand_pmecc_init()
1107 chip->options |= NAND_NO_SUBPAGE_WRITE; in atmel_nand_pmecc_init()
1119 nc = to_nand_controller(chip->controller); in atmel_nand_ecc_init()
1121 switch (chip->ecc.mode) { in atmel_nand_ecc_init()
1134 chip->ecc.read_page = atmel_nand_pmecc_read_page; in atmel_nand_ecc_init()
1135 chip->ecc.write_page = atmel_nand_pmecc_write_page; in atmel_nand_ecc_init()
1136 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; in atmel_nand_ecc_init()
1137 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; in atmel_nand_ecc_init()
1142 dev_err(nc->dev, "Unsupported ECC mode: %d\n", in atmel_nand_ecc_init()
1143 chip->ecc.mode); in atmel_nand_ecc_init()
1144 return -ENOTSUPP; in atmel_nand_ecc_init()
1158 if (chip->ecc.mode != NAND_ECC_HW) in atmel_hsmc_nand_ecc_init()
1161 /* Adjust the ECC operations for the HSMC IP. */ in atmel_hsmc_nand_ecc_init()
1162 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; in atmel_hsmc_nand_ecc_init()
1163 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; in atmel_hsmc_nand_ecc_init()
1164 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; in atmel_hsmc_nand_ecc_init()
1165 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; in atmel_hsmc_nand_ecc_init()
1170 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, in atmel_smc_nand_prepare_smcconf() argument
1178 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_prepare_smcconf()
1181 if (conf->type != NAND_SDR_IFACE) in atmel_smc_nand_prepare_smcconf()
1182 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1185 * tRC < 30ns implies EDO mode. This controller does not support this in atmel_smc_nand_prepare_smcconf()
1186 * mode. in atmel_smc_nand_prepare_smcconf()
1188 if (conf->timings.sdr.tRC_min < 30000) in atmel_smc_nand_prepare_smcconf()
1189 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1193 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); in atmel_smc_nand_prepare_smcconf()
1201 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1209 * The write setup timing depends on the operation done on the NAND. in atmel_smc_nand_prepare_smcconf()
1217 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE in atmel_smc_nand_prepare_smcconf()
1219 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, in atmel_smc_nand_prepare_smcconf()
1220 conf->timings.sdr.tALS_min); in atmel_smc_nand_prepare_smcconf()
1221 timeps = max(timeps, conf->timings.sdr.tDS_min); in atmel_smc_nand_prepare_smcconf()
1223 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; in atmel_smc_nand_prepare_smcconf()
1232 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1236 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, in atmel_smc_nand_prepare_smcconf()
1237 conf->timings.sdr.tALH_min); in atmel_smc_nand_prepare_smcconf()
1238 timeps = max3(timeps, conf->timings.sdr.tDH_min, in atmel_smc_nand_prepare_smcconf()
1239 conf->timings.sdr.tWH_min); in atmel_smc_nand_prepare_smcconf()
1250 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1259 * transfer to the NAND. The only way to guarantee that is to have the in atmel_smc_nand_prepare_smcconf()
1271 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1275 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); in atmel_smc_nand_prepare_smcconf()
1280 * TDF = tRHZ - NRD_HOLD in atmel_smc_nand_prepare_smcconf()
1282 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1283 ncycles -= totalcycles; in atmel_smc_nand_prepare_smcconf()
1288 * Just take the max value in this case and hope that the NAND is more in atmel_smc_nand_prepare_smcconf()
1296 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | in atmel_smc_nand_prepare_smcconf()
1304 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1320 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1329 * transfer from the NAND. The only way to guarantee that is to have in atmel_smc_nand_prepare_smcconf()
1340 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1347 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1355 * accept the -ERANGE return code. in atmel_smc_nand_prepare_smcconf()
1362 if (ret && ret != -ERANGE) in atmel_smc_nand_prepare_smcconf()
1365 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1372 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1379 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1387 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; in atmel_smc_nand_prepare_smcconf()
1390 if (nand->base.options & NAND_BUSWIDTH_16) in atmel_smc_nand_prepare_smcconf()
1391 smcconf->mode |= ATMEL_SMC_MODE_DBW_16; in atmel_smc_nand_prepare_smcconf()
1394 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | in atmel_smc_nand_prepare_smcconf()
1400 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand, in atmel_smc_nand_setup_data_interface() argument
1409 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_setup_data_interface()
1411 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_smc_nand_setup_data_interface()
1418 cs = &nand->cs[csline]; in atmel_smc_nand_setup_data_interface()
1419 cs->smcconf = smcconf; in atmel_smc_nand_setup_data_interface()
1420 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); in atmel_smc_nand_setup_data_interface()
1425 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand, in atmel_hsmc_nand_setup_data_interface() argument
1434 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_setup_data_interface()
1436 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_hsmc_nand_setup_data_interface()
1443 cs = &nand->cs[csline]; in atmel_hsmc_nand_setup_data_interface()
1444 cs->smcconf = smcconf; in atmel_hsmc_nand_setup_data_interface()
1446 if (cs->rb.type == ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_setup_data_interface()
1447 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); in atmel_hsmc_nand_setup_data_interface()
1449 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, in atmel_hsmc_nand_setup_data_interface()
1450 &cs->smcconf); in atmel_hsmc_nand_setup_data_interface()
1458 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_setup_data_interface() local
1461 nc = to_nand_controller(nand->base.controller); in atmel_nand_setup_data_interface()
1463 if (csline >= nand->numcs || in atmel_nand_setup_data_interface()
1465 return -EINVAL; in atmel_nand_setup_data_interface()
1467 return nc->caps->ops->setup_data_interface(nand, csline, conf); in atmel_nand_setup_data_interface()
1471 struct atmel_nand *nand) in atmel_nand_init() argument
1473 struct nand_chip *chip = &nand->base; in atmel_nand_init()
1476 mtd->dev.parent = nc->dev; in atmel_nand_init()
1477 nand->base.controller = &nc->base; in atmel_nand_init()
1479 chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl; in atmel_nand_init()
1480 chip->legacy.read_byte = atmel_nand_read_byte; in atmel_nand_init()
1481 chip->legacy.write_byte = atmel_nand_write_byte; in atmel_nand_init()
1482 chip->legacy.read_buf = atmel_nand_read_buf; in atmel_nand_init()
1483 chip->legacy.write_buf = atmel_nand_write_buf; in atmel_nand_init()
1484 chip->legacy.select_chip = atmel_nand_select_chip; in atmel_nand_init()
1486 if (!nc->mck || !nc->caps->ops->setup_data_interface) in atmel_nand_init()
1487 chip->options |= NAND_KEEP_TIMINGS; in atmel_nand_init()
1490 chip->legacy.chip_delay = 40; in atmel_nand_init()
1496 if (nc->dmac) in atmel_nand_init()
1497 chip->options |= NAND_USE_BOUNCE_BUFFER; in atmel_nand_init()
1499 /* Default to HW ECC if pmecc is available. */ in atmel_nand_init()
1500 if (nc->pmecc) in atmel_nand_init()
1501 chip->ecc.mode = NAND_ECC_HW; in atmel_nand_init()
1505 struct atmel_nand *nand) in atmel_smc_nand_init() argument
1507 struct nand_chip *chip = &nand->base; in atmel_smc_nand_init()
1511 atmel_nand_init(nc, nand); in atmel_smc_nand_init()
1513 smc_nc = to_smc_nand_controller(chip->controller); in atmel_smc_nand_init()
1514 if (!smc_nc->ebi_csa_regmap) in atmel_smc_nand_init()
1517 /* Attach the CS to the NAND Flash logic. */ in atmel_smc_nand_init()
1518 for (i = 0; i < nand->numcs; i++) in atmel_smc_nand_init()
1519 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1520 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1521 BIT(nand->cs[i].id), BIT(nand->cs[i].id)); in atmel_smc_nand_init()
1523 if (smc_nc->ebi_csa->nfd0_on_d16) in atmel_smc_nand_init()
1524 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1525 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1526 smc_nc->ebi_csa->nfd0_on_d16, in atmel_smc_nand_init()
1527 smc_nc->ebi_csa->nfd0_on_d16); in atmel_smc_nand_init()
1531 struct atmel_nand *nand) in atmel_hsmc_nand_init() argument
1533 struct nand_chip *chip = &nand->base; in atmel_hsmc_nand_init()
1535 atmel_nand_init(nc, nand); in atmel_hsmc_nand_init()
1538 chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl; in atmel_hsmc_nand_init()
1539 chip->legacy.select_chip = atmel_hsmc_nand_select_chip; in atmel_hsmc_nand_init()
1542 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) in atmel_nand_controller_remove_nand() argument
1544 struct nand_chip *chip = &nand->base; in atmel_nand_controller_remove_nand()
1553 list_del(&nand->node); in atmel_nand_controller_remove_nand()
1562 struct atmel_nand *nand; in atmel_nand_create() local
1569 dev_err(nc->dev, "Missing or invalid reg property\n"); in atmel_nand_create()
1570 return ERR_PTR(-EINVAL); in atmel_nand_create()
1573 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL); in atmel_nand_create()
1574 if (!nand) { in atmel_nand_create()
1575 dev_err(nc->dev, "Failed to allocate NAND object\n"); in atmel_nand_create()
1576 return ERR_PTR(-ENOMEM); in atmel_nand_create()
1579 nand->numcs = numcs; in atmel_nand_create()
1581 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0, in atmel_nand_create()
1582 &np->fwnode, GPIOD_IN, in atmel_nand_create()
1583 "nand-det"); in atmel_nand_create()
1584 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1585 dev_err(nc->dev, in atmel_nand_create()
1592 nand->cdgpio = gpio; in atmel_nand_create()
1600 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1608 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1613 nand->cs[i].id = val; in atmel_nand_create()
1615 nand->cs[i].io.dma = res.start; in atmel_nand_create()
1616 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res); in atmel_nand_create()
1617 if (IS_ERR(nand->cs[i].io.virt)) in atmel_nand_create()
1618 return ERR_CAST(nand->cs[i].io.virt); in atmel_nand_create()
1622 return ERR_PTR(-EINVAL); in atmel_nand_create()
1624 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; in atmel_nand_create()
1625 nand->cs[i].rb.id = val; in atmel_nand_create()
1627 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, in atmel_nand_create()
1628 "rb", i, &np->fwnode, in atmel_nand_create()
1629 GPIOD_IN, "nand-rb"); in atmel_nand_create()
1630 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1631 dev_err(nc->dev, in atmel_nand_create()
1638 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_create()
1639 nand->cs[i].rb.gpio = gpio; in atmel_nand_create()
1643 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs", in atmel_nand_create()
1644 i, &np->fwnode, in atmel_nand_create()
1646 "nand-cs"); in atmel_nand_create()
1647 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1648 dev_err(nc->dev, in atmel_nand_create()
1655 nand->cs[i].csgpio = gpio; in atmel_nand_create()
1658 nand_set_flash_node(&nand->base, np); in atmel_nand_create()
1660 return nand; in atmel_nand_create()
1665 struct atmel_nand *nand) in atmel_nand_controller_add_nand() argument
1667 struct nand_chip *chip = &nand->base; in atmel_nand_controller_add_nand()
1671 /* No card inserted, skip this NAND. */ in atmel_nand_controller_add_nand()
1672 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) { in atmel_nand_controller_add_nand()
1673 dev_info(nc->dev, "No SmartMedia card inserted.\n"); in atmel_nand_controller_add_nand()
1677 nc->caps->ops->nand_init(nc, nand); in atmel_nand_controller_add_nand()
1679 ret = nand_scan(chip, nand->numcs); in atmel_nand_controller_add_nand()
1681 dev_err(nc->dev, "NAND scan failed: %d\n", ret); in atmel_nand_controller_add_nand()
1687 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret); in atmel_nand_controller_add_nand()
1692 list_add_tail(&nand->node, &nc->chips); in atmel_nand_controller_add_nand()
1700 struct atmel_nand *nand, *tmp; in atmel_nand_controller_remove_nands() local
1703 list_for_each_entry_safe(nand, tmp, &nc->chips, node) { in atmel_nand_controller_remove_nands()
1704 ret = atmel_nand_controller_remove_nand(nand); in atmel_nand_controller_remove_nands()
1715 struct device *dev = nc->dev; in atmel_nand_controller_legacy_add_nands()
1717 struct atmel_nand *nand; in atmel_nand_controller_legacy_add_nands() local
1722 * Legacy bindings only allow connecting a single NAND with a unique CS in atmel_nand_controller_legacy_add_nands()
1725 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs), in atmel_nand_controller_legacy_add_nands()
1727 if (!nand) in atmel_nand_controller_legacy_add_nands()
1728 return -ENOMEM; in atmel_nand_controller_legacy_add_nands()
1730 nand->numcs = 1; in atmel_nand_controller_legacy_add_nands()
1733 nand->cs[0].io.virt = devm_ioremap_resource(dev, res); in atmel_nand_controller_legacy_add_nands()
1734 if (IS_ERR(nand->cs[0].io.virt)) in atmel_nand_controller_legacy_add_nands()
1735 return PTR_ERR(nand->cs[0].io.virt); in atmel_nand_controller_legacy_add_nands()
1737 nand->cs[0].io.dma = res->start; in atmel_nand_controller_legacy_add_nands()
1744 * If one wants to connect a NAND to a different CS line, he will in atmel_nand_controller_legacy_add_nands()
1747 nand->cs[0].id = 3; in atmel_nand_controller_legacy_add_nands()
1758 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_controller_legacy_add_nands()
1759 nand->cs[0].rb.gpio = gpio; in atmel_nand_controller_legacy_add_nands()
1770 nand->cs[0].csgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1773 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN); in atmel_nand_controller_legacy_add_nands()
1781 nand->cdgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1783 nand_set_flash_node(&nand->base, nc->dev->of_node); in atmel_nand_controller_legacy_add_nands()
1785 return atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_legacy_add_nands()
1791 struct device *dev = nc->dev; in atmel_nand_controller_add_nands()
1796 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_add_nands()
1799 np = dev->of_node; in atmel_nand_controller_add_nands()
1801 ret = of_property_read_u32(np, "#address-cells", &val); in atmel_nand_controller_add_nands()
1803 dev_err(dev, "missing #address-cells property\n"); in atmel_nand_controller_add_nands()
1809 ret = of_property_read_u32(np, "#size-cells", &val); in atmel_nand_controller_add_nands()
1811 dev_err(dev, "missing #size-cells property\n"); in atmel_nand_controller_add_nands()
1818 struct atmel_nand *nand; in atmel_nand_controller_add_nands() local
1820 nand = atmel_nand_create(nc, nand_np, reg_cells); in atmel_nand_controller_add_nands()
1821 if (IS_ERR(nand)) { in atmel_nand_controller_add_nands()
1822 ret = PTR_ERR(nand); in atmel_nand_controller_add_nands()
1826 ret = atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_add_nands()
1841 if (nc->dmac) in atmel_nand_controller_cleanup()
1842 dma_release_channel(nc->dmac); in atmel_nand_controller_cleanup()
1844 clk_put(nc->mck); in atmel_nand_controller_cleanup()
1882 .compatible = "atmel,at91sam9260-matrix",
1886 .compatible = "atmel,at91sam9261-matrix",
1890 .compatible = "atmel,at91sam9263-matrix",
1894 .compatible = "atmel,at91sam9rl-matrix",
1898 .compatible = "atmel,at91sam9g45-matrix",
1902 .compatible = "atmel,at91sam9n12-matrix",
1906 .compatible = "atmel,at91sam9x5-matrix",
1910 .compatible = "microchip,sam9x60-sfr",
1918 struct atmel_nand_controller *nc = to_nand_controller(chip->controller); in atmel_nand_attach_chip()
1919 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_attach_chip() local
1923 ret = nc->caps->ops->ecc_init(chip); in atmel_nand_attach_chip()
1927 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) { in atmel_nand_attach_chip()
1933 mtd->name = "atmel_nand"; in atmel_nand_attach_chip()
1934 } else if (!mtd->name) { in atmel_nand_attach_chip()
1938 * should define the following property in your nand node: in atmel_nand_attach_chip()
1942 * This way, mtd->name will be set by the core when in atmel_nand_attach_chip()
1945 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL, in atmel_nand_attach_chip()
1946 "%s:nand.%d", dev_name(nc->dev), in atmel_nand_attach_chip()
1947 nand->cs[0].id); in atmel_nand_attach_chip()
1948 if (!mtd->name) { in atmel_nand_attach_chip()
1949 dev_err(nc->dev, "Failed to allocate mtd->name\n"); in atmel_nand_attach_chip()
1950 return -ENOMEM; in atmel_nand_attach_chip()
1966 struct device *dev = &pdev->dev; in atmel_nand_controller_init()
1967 struct device_node *np = dev->of_node; in atmel_nand_controller_init()
1970 nand_controller_init(&nc->base); in atmel_nand_controller_init()
1971 nc->base.ops = &atmel_nand_controller_ops; in atmel_nand_controller_init()
1972 INIT_LIST_HEAD(&nc->chips); in atmel_nand_controller_init()
1973 nc->dev = dev; in atmel_nand_controller_init()
1974 nc->caps = caps; in atmel_nand_controller_init()
1978 nc->pmecc = devm_atmel_pmecc_get(dev); in atmel_nand_controller_init()
1979 if (IS_ERR(nc->pmecc)) { in atmel_nand_controller_init()
1980 ret = PTR_ERR(nc->pmecc); in atmel_nand_controller_init()
1981 if (ret != -EPROBE_DEFER) in atmel_nand_controller_init()
1987 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { in atmel_nand_controller_init()
1993 nc->dmac = dma_request_channel(mask, NULL, NULL); in atmel_nand_controller_init()
1994 if (!nc->dmac) in atmel_nand_controller_init()
1995 dev_err(nc->dev, "Failed to request DMA channel\n"); in atmel_nand_controller_init()
1999 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_init()
2002 nc->mck = of_clk_get(dev->parent->of_node, 0); in atmel_nand_controller_init()
2003 if (IS_ERR(nc->mck)) { in atmel_nand_controller_init()
2005 return PTR_ERR(nc->mck); in atmel_nand_controller_init()
2008 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_nand_controller_init()
2011 return -EINVAL; in atmel_nand_controller_init()
2014 nc->smc = syscon_node_to_regmap(np); in atmel_nand_controller_init()
2016 if (IS_ERR(nc->smc)) { in atmel_nand_controller_init()
2017 ret = PTR_ERR(nc->smc); in atmel_nand_controller_init()
2028 struct device *dev = nc->base.dev; in atmel_smc_nand_controller_init()
2034 if (nc->base.caps->legacy_of_bindings) in atmel_smc_nand_controller_init()
2037 np = of_parse_phandle(dev->parent->of_node, in atmel_smc_nand_controller_init()
2038 nc->base.caps->ebi_csa_regmap_name, 0); in atmel_smc_nand_controller_init()
2048 nc->ebi_csa_regmap = syscon_node_to_regmap(np); in atmel_smc_nand_controller_init()
2050 if (IS_ERR(nc->ebi_csa_regmap)) { in atmel_smc_nand_controller_init()
2051 ret = PTR_ERR(nc->ebi_csa_regmap); in atmel_smc_nand_controller_init()
2056 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; in atmel_smc_nand_controller_init()
2059 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 in atmel_smc_nand_controller_init()
2060 * add 4 to ->ebi_csa->offs. in atmel_smc_nand_controller_init()
2062 if (of_device_is_compatible(dev->parent->of_node, in atmel_smc_nand_controller_init()
2063 "atmel,at91sam9263-ebi1")) in atmel_smc_nand_controller_init()
2064 nc->ebi_csa->offs += 4; in atmel_smc_nand_controller_init()
2078 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_legacy_init()
2084 nand_np = dev->of_node; in atmel_hsmc_nand_controller_legacy_init()
2085 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); in atmel_hsmc_nand_controller_legacy_init()
2087 dev_err(dev, "Could not find device node for sama5d3-nfc\n"); in atmel_hsmc_nand_controller_legacy_init()
2088 return -ENODEV; in atmel_hsmc_nand_controller_legacy_init()
2091 nc->clk = of_clk_get(nfc_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2092 if (IS_ERR(nc->clk)) { in atmel_hsmc_nand_controller_legacy_init()
2093 ret = PTR_ERR(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2099 ret = clk_prepare_enable(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2106 nc->irq = of_irq_get(nand_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2107 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_legacy_init()
2108 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_legacy_init()
2109 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_legacy_init()
2128 regmap_conf.name = "nfc-io"; in atmel_hsmc_nand_controller_legacy_init()
2129 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2130 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2131 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_legacy_init()
2132 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_legacy_init()
2152 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2153 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2154 if (IS_ERR(nc->base.smc)) { in atmel_hsmc_nand_controller_legacy_init()
2155 ret = PTR_ERR(nc->base.smc); in atmel_hsmc_nand_controller_legacy_init()
2168 nc->sram.virt = devm_ioremap_resource(dev, &res); in atmel_hsmc_nand_controller_legacy_init()
2169 if (IS_ERR(nc->sram.virt)) { in atmel_hsmc_nand_controller_legacy_init()
2170 ret = PTR_ERR(nc->sram.virt); in atmel_hsmc_nand_controller_legacy_init()
2174 nc->sram.dma = res.start; in atmel_hsmc_nand_controller_legacy_init()
2185 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_init()
2189 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_hsmc_nand_controller_init()
2192 return -EINVAL; in atmel_hsmc_nand_controller_init()
2195 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); in atmel_hsmc_nand_controller_init()
2197 nc->irq = of_irq_get(np, 0); in atmel_hsmc_nand_controller_init()
2199 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_init()
2200 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_init()
2201 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_init()
2207 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0); in atmel_hsmc_nand_controller_init()
2209 dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); in atmel_hsmc_nand_controller_init()
2210 return -EINVAL; in atmel_hsmc_nand_controller_init()
2213 nc->io = syscon_node_to_regmap(np); in atmel_hsmc_nand_controller_init()
2215 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_init()
2216 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_init()
2221 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, in atmel_hsmc_nand_controller_init()
2222 "atmel,nfc-sram", 0); in atmel_hsmc_nand_controller_init()
2223 if (!nc->sram.pool) { in atmel_hsmc_nand_controller_init()
2224 dev_err(nc->base.dev, "Missing SRAM\n"); in atmel_hsmc_nand_controller_init()
2225 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2228 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool, in atmel_hsmc_nand_controller_init()
2230 &nc->sram.dma); in atmel_hsmc_nand_controller_init()
2231 if (!nc->sram.virt) { in atmel_hsmc_nand_controller_init()
2232 dev_err(nc->base.dev, in atmel_hsmc_nand_controller_init()
2234 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2251 if (hsmc_nc->sram.pool) in atmel_hsmc_nand_controller_remove()
2252 gen_pool_free(hsmc_nc->sram.pool, in atmel_hsmc_nand_controller_remove()
2253 (unsigned long)hsmc_nc->sram.virt, in atmel_hsmc_nand_controller_remove()
2256 if (hsmc_nc->clk) { in atmel_hsmc_nand_controller_remove()
2257 clk_disable_unprepare(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2258 clk_put(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2269 struct device *dev = &pdev->dev; in atmel_hsmc_nand_controller_probe()
2275 return -ENOMEM; in atmel_hsmc_nand_controller_probe()
2277 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_hsmc_nand_controller_probe()
2281 if (caps->legacy_of_bindings) in atmel_hsmc_nand_controller_probe()
2290 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_hsmc_nand_controller_probe()
2291 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt, in atmel_hsmc_nand_controller_probe()
2301 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_controller_probe()
2304 ret = atmel_nand_controller_add_nands(&nc->base); in atmel_hsmc_nand_controller_probe()
2311 atmel_hsmc_nand_controller_remove(&nc->base); in atmel_hsmc_nand_controller_probe()
2343 struct device *dev = &pdev->dev; in atmel_smc_nand_controller_probe()
2349 return -ENOMEM; in atmel_smc_nand_controller_probe()
2351 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_smc_nand_controller_probe()
2359 return atmel_nand_controller_add_nands(&nc->base); in atmel_smc_nand_controller_probe()
2378 * from re-using atmel_smc_nand_setup_data_interface() for the
2379 * ->setup_data_interface() hook.
2381 * ->setup_data_interface() unassigned.
2460 .compatible = "atmel,at91rm9200-nand-controller",
2464 .compatible = "atmel,at91sam9260-nand-controller",
2468 .compatible = "atmel,at91sam9261-nand-controller",
2472 .compatible = "atmel,at91sam9g45-nand-controller",
2476 .compatible = "atmel,sama5d3-nand-controller",
2480 .compatible = "microchip,sam9x60-nand-controller",
2485 .compatible = "atmel,at91rm9200-nand",
2489 .compatible = "atmel,sama5d4-nand",
2493 .compatible = "atmel,sama5d2-nand",
2504 if (pdev->id_entry) in atmel_nand_controller_probe()
2505 caps = (void *)pdev->id_entry->driver_data; in atmel_nand_controller_probe()
2507 caps = of_device_get_match_data(&pdev->dev); in atmel_nand_controller_probe()
2510 dev_err(&pdev->dev, "Could not retrieve NFC caps\n"); in atmel_nand_controller_probe()
2511 return -EINVAL; in atmel_nand_controller_probe()
2514 if (caps->legacy_of_bindings) { in atmel_nand_controller_probe()
2522 nfc_node = of_get_compatible_child(pdev->dev.of_node, in atmel_nand_controller_probe()
2523 "atmel,sama5d3-nfc"); in atmel_nand_controller_probe()
2531 * at91rm9200 controller, the atmel,nand-has-dma specify that in atmel_nand_controller_probe()
2535 if (!caps->has_dma && in atmel_nand_controller_probe()
2536 of_property_read_bool(pdev->dev.of_node, in atmel_nand_controller_probe()
2537 "atmel,nand-has-dma")) in atmel_nand_controller_probe()
2542 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're in atmel_nand_controller_probe()
2545 of_property_read_u32(pdev->dev.of_node, in atmel_nand_controller_probe()
2546 "atmel,nand-addr-offset", &ale_offs); in atmel_nand_controller_probe()
2551 return caps->ops->probe(pdev, caps); in atmel_nand_controller_probe()
2558 return nc->caps->ops->remove(nc); in atmel_nand_controller_remove()
2564 struct atmel_nand *nand; in atmel_nand_controller_resume() local
2566 if (nc->pmecc) in atmel_nand_controller_resume()
2567 atmel_pmecc_reset(nc->pmecc); in atmel_nand_controller_resume()
2569 list_for_each_entry(nand, &nc->chips, node) { in atmel_nand_controller_resume()
2572 for (i = 0; i < nand->numcs; i++) in atmel_nand_controller_resume()
2573 nand_reset(&nand->base, i); in atmel_nand_controller_resume()
2584 .name = "atmel-nand-controller",
2594 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2595 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2596 MODULE_ALIAS("platform:atmel-nand-controller");