Lines Matching defs:sdhci_host
372 struct sdhci_host { struct
374 const char *hw_name; /* Hardware bus name */
376 unsigned int quirks; /* Deviations from spec. */
441 unsigned int quirks2; /* More deviations from spec. */
486 int irq; /* Device IRQ */
487 void __iomem *ioaddr; /* Mapped address */
488 char *bounce_buffer; /* For packing SDMA reads/writes */
489 dma_addr_t bounce_addr;
490 unsigned int bounce_buffer_size;
492 const struct sdhci_ops *ops; /* Low level hw interface */
495 struct mmc_host *mmc; /* MMC structure */
496 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
497 u64 dma_mask; /* custom DMA mask */
500 struct led_classdev led; /* LED control */
501 char led_name[32];
504 spinlock_t lock; /* Mutex */
506 int flags; /* Host attributes */
521 unsigned int version; /* SDHCI spec. version */
523 unsigned int max_clk; /* Max possible freq (MHz) */
524 unsigned int timeout_clk; /* Timeout freq (KHz) */
525 unsigned int clk_mul; /* Clock Muliplier value */
527 unsigned int clock; /* Current clock (MHz) */
528 u8 pwr; /* Current voltage */
530 bool runtime_suspended; /* Host is runtime suspended */
531 bool bus_on; /* Bus power prevents runtime suspend */
532 bool preset_enabled; /* Preset is enabled */
533 bool pending_reset; /* Cmd/data reset is pending */
534 bool irq_wake_enabled; /* IRQ wakeup is enabled */
535 bool v4_mode; /* Host Version 4 Enable */
537 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
538 struct mmc_command *cmd; /* Current command */
539 struct mmc_command *data_cmd; /* Current data command */
540 struct mmc_data *data; /* Current data request */
541 unsigned int data_early:1; /* Data finished before cmd */
543 struct sg_mapping_iter sg_miter; /* SG state for PIO */
544 unsigned int blocks; /* remaining PIO blocks */
546 int sg_count; /* Mapped sg entries */
548 void *adma_table; /* ADMA descriptor table */
549 void *align_buffer; /* Bounce buffer */
551 size_t adma_table_sz; /* ADMA descriptor table size */
552 size_t align_buffer_sz; /* Bounce buffer size */
554 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
555 dma_addr_t align_addr; /* Mapped bounce buffer */
557 unsigned int desc_sz; /* ADMA descriptor size */
559 struct workqueue_struct *complete_wq; /* Request completion wq */
560 struct work_struct complete_work; /* Request completion work */
562 struct timer_list timer; /* Timer for timeouts */
563 struct timer_list data_timer; /* Timer for data timeouts */
565 u32 caps; /* CAPABILITY_0 */
566 u32 caps1; /* CAPABILITY_1 */
567 bool read_caps; /* Capability flags have been read */
569 unsigned int ocr_avail_sdio; /* OCR bit masks */
570 unsigned int ocr_avail_sd;
571 unsigned int ocr_avail_mmc;
572 u32 ocr_mask; /* available voltages */
574 unsigned timing; /* Current timing */
576 u32 thread_isr;
579 u32 ier;
581 bool cqe_on; /* CQE is operating */
582 u32 cqe_ier; /* CQE interrupt mask */
583 u32 cqe_err_ier; /* CQE error interrupt mask */
585 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
586 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
611 u32 (*read_l)(struct sdhci_host *host, int reg); argument