Lines Matching defs:msdc_host

388 struct msdc_host {  struct
389 	struct device *dev;
390 	const struct mtk_mmc_compatible *dev_comp;
391 	struct mmc_host *mmc;	/* mmc structure */
392 	int cmd_rsp;
394 	spinlock_t lock;
395 	struct mmc_request *mrq;
396 	struct mmc_command *cmd;
397 	struct mmc_data *data;
398 	int error;
400 	void __iomem *base;		/* host base address */
401 	void __iomem *top_base;		/* host top register base address */
403 	struct msdc_dma dma;	/* dma channel */
404 	u64 dma_mask;
406 	u32 timeout_ns;		/* data timeout ns */
407 	u32 timeout_clks;	/* data timeout clks */
409 	struct pinctrl *pinctrl;
410 	struct pinctrl_state *pins_default;
411 	struct pinctrl_state *pins_uhs;
412 	struct delayed_work req_timeout;
413 	int irq;		/* host interrupt */
415 	struct clk *src_clk;	/* msdc source clock */
416 	struct clk *h_clk;      /* msdc h_clk */
417 	struct clk *bus_clk;	/* bus clock which used to access register */
418 	struct clk *src_clk_cg; /* msdc source clock control gate */
419 	u32 mclk;		/* mmc subsystem clock frequency */
420 	u32 src_clk_freq;	/* source clock frequency */
421 	unsigned char timing;
422 	bool vqmmc_enabled;
423 	u32 latch_ck;
424 	u32 hs400_ds_delay;
425 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
426 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
427 	bool hs400_cmd_resp_sel_rising;
429 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
430 	bool internal_cd;	/* Use internal card-detect logic */
431 	struct msdc_save_para save_para; /* used when gate HCLK */
432 	struct msdc_tune_para def_tune_para; /* default tune setting */
433 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */