Lines Matching refs:dev
58 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
60 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
69 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
71 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
81 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
85 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
86 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
98 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
102 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
103 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
114 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
116 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
117 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
127 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
130 mei_hcsr_write(dev, reg); in mei_hcsr_set()
138 static inline void mei_hcsr_set_hig(struct mei_device *dev) in mei_hcsr_set_hig() argument
142 hcsr = mei_hcsr_read(dev) | H_IG; in mei_hcsr_set_hig()
143 mei_hcsr_set(dev, hcsr); in mei_hcsr_set_hig()
153 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
157 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
158 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
169 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
171 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
172 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
183 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
186 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_fw_status()
187 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
199 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", in mei_me_fw_status()
214 static void mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
216 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_hw_config()
217 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
221 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
226 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_hw_config()
232 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
246 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
248 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
265 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) in me_intr_disable() argument
268 mei_hcsr_set(dev, hcsr); in me_intr_disable()
277 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) in me_intr_clear() argument
280 mei_hcsr_write(dev, hcsr); in me_intr_clear()
288 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
290 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
292 me_intr_clear(dev, hcsr); in mei_me_intr_clear()
299 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
301 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_enable()
304 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
312 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
314 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
316 me_intr_disable(dev, hcsr); in mei_me_intr_disable()
324 static void mei_me_synchronize_irq(struct mei_device *dev) in mei_me_synchronize_irq() argument
326 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_synchronize_irq()
336 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
338 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
342 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
350 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
352 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
355 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
364 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
366 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
377 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
379 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
390 static bool mei_me_hw_is_resetting(struct mei_device *dev) in mei_me_hw_is_resetting() argument
392 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_resetting()
404 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
406 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
407 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
408 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
410 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
411 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
412 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
416 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
417 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
427 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
429 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
433 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
435 mei_me_host_set_ready(dev); in mei_me_hw_start()
447 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
452 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
467 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
469 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
479 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
481 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_empty_slots()
484 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
501 static u32 mei_me_hbuf_depth(const struct mei_device *dev) in mei_me_hbuf_depth() argument
503 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_depth()
519 static int mei_me_hbuf_write(struct mei_device *dev, in mei_me_hbuf_write() argument
532 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_me_hbuf_write()
534 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_hbuf_write()
535 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); in mei_me_hbuf_write()
546 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
550 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
557 mei_me_hcbww_write(dev, reg); in mei_me_hbuf_write()
560 mei_hcsr_set_hig(dev); in mei_me_hbuf_write()
561 if (!mei_me_hw_is_ready(dev)) in mei_me_hbuf_write()
574 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
580 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
590 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
603 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
609 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
612 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
617 mei_hcsr_set_hig(dev); in mei_me_read_slots()
626 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
628 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
632 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
636 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
645 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
647 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
651 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
657 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
668 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
670 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
674 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
676 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
680 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
681 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
682 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_enter_sync()
683 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
685 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
686 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
692 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
705 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
707 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
711 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
714 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
716 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
718 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
719 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
720 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
721 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
724 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
729 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
730 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
734 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
735 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
736 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
737 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
739 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
745 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
758 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
760 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
761 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
771 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
773 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
774 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
782 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
788 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
791 dev->version.major_version, in mei_me_pg_is_enabled()
792 dev->version.minor_version, in mei_me_pg_is_enabled()
807 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
809 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
816 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
818 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
829 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
831 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
835 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
837 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
848 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
850 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
856 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
859 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
865 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
867 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
872 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
873 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
874 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); in mei_me_d0i3_enter_sync()
875 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
877 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
883 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
885 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
887 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
892 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
893 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
894 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); in mei_me_d0i3_enter_sync()
895 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
897 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
898 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
909 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
910 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
924 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
926 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
929 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
932 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
936 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
939 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
940 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
951 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
953 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
958 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
960 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
963 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
968 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
970 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
975 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
976 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
977 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_d0i3_exit_sync()
978 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
980 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
981 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
992 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
994 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
1004 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
1006 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
1008 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
1011 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
1013 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
1014 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
1023 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) in mei_me_d0i3_intr() argument
1025 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
1027 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
1029 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
1032 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
1037 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
1038 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
1044 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
1053 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
1054 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
1064 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) in mei_me_pg_intr() argument
1066 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1069 mei_me_d0i3_intr(dev, intr_source); in mei_me_pg_intr()
1071 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1081 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1083 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1086 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1088 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1098 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1100 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1103 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1105 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1116 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1118 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1123 mei_me_intr_enable(dev); in mei_me_hw_reset()
1125 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1131 pm_runtime_set_active(dev->dev); in mei_me_hw_reset()
1133 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1140 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1142 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1143 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1151 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1152 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1158 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1161 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1164 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1167 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1169 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1187 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1190 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1194 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); in mei_me_irq_quick_handler()
1197 me_intr_disable(dev, hcsr); in mei_me_irq_quick_handler()
1213 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1219 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1221 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1223 hcsr = mei_hcsr_read(dev); in mei_me_irq_thread_handler()
1224 me_intr_clear(dev, hcsr); in mei_me_irq_thread_handler()
1229 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1230 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_me_irq_thread_handler()
1231 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1235 if (mei_me_hw_is_resetting(dev)) in mei_me_irq_thread_handler()
1236 mei_hcsr_set_hig(dev); in mei_me_irq_thread_handler()
1238 mei_me_pg_intr(dev, me_intr_src(hcsr)); in mei_me_irq_thread_handler()
1241 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1242 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1243 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1244 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1245 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1247 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1252 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1254 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1255 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); in mei_me_irq_thread_handler()
1264 (dev->dev_state != MEI_DEV_RESETTING && in mei_me_irq_thread_handler()
1265 dev->dev_state != MEI_DEV_POWER_DOWN)) { in mei_me_irq_thread_handler()
1266 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", in mei_me_irq_thread_handler()
1268 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1273 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1280 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1281 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1282 rets = mei_irq_write_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1283 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1286 mei_irq_compl_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1289 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1290 mei_me_intr_enable(dev); in mei_me_irq_thread_handler()
1291 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1331 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); in mei_me_fw_type_nm()
1350 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_fw_type_sps()
1472 struct mei_device *dev; in mei_me_dev_init() local
1476 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) + in mei_me_dev_init()
1478 if (!dev) in mei_me_dev_init()
1481 hw = to_me_hw(dev); in mei_me_dev_init()
1484 dev->dr_dscr[i].size = cfg->dma_size[i]; in mei_me_dev_init()
1486 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); in mei_me_dev_init()
1489 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported; in mei_me_dev_init()
1491 return dev; in mei_me_dev_init()