16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)  in rts5249_get_ic_version()  argument
20 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);  in rts5249_get_ic_version()
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)  in rts5249_fill_driving()  argument
42 		drive_sel = pcr->sd30_drive_sel_3v3;  in rts5249_fill_driving()
45 		drive_sel = pcr->sd30_drive_sel_1v8;  in rts5249_fill_driving()
48 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,  in rts5249_fill_driving()
50 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,  in rts5249_fill_driving()
52 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,  in rts5249_fill_driving()
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)  in rtsx_base_fetch_vendor_settings()  argument
60 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);  in rtsx_base_fetch_vendor_settings()
61 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);  in rtsx_base_fetch_vendor_settings()
64 		pcr_dbg(pcr, "skip fetch vendor setting\n");  in rtsx_base_fetch_vendor_settings()
68 	pcr->aspm_en = rtsx_reg_to_aspm(reg);  in rtsx_base_fetch_vendor_settings()
69 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);  in rtsx_base_fetch_vendor_settings()
70 	pcr->card_drive_sel &= 0x3F;  in rtsx_base_fetch_vendor_settings()
71 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);  in rtsx_base_fetch_vendor_settings()
73 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);  in rtsx_base_fetch_vendor_settings()
74 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);  in rtsx_base_fetch_vendor_settings()
75 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);  in rtsx_base_fetch_vendor_settings()
77 		pcr->flags |= PCR_REVERSE_SOCKET;  in rtsx_base_fetch_vendor_settings()
80 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)  in rtsx_base_force_power_down()  argument
83 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);  in rtsx_base_force_power_down()
84 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);  in rtsx_base_force_power_down()
85 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);  in rtsx_base_force_power_down()
88 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,  in rtsx_base_force_power_down()
91 	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);  in rtsx_base_force_power_down()
94 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)  in rts5249_init_from_cfg()  argument
96 	struct rtsx_cr_option *option = &(pcr->option);  in rts5249_init_from_cfg()
99 	if (CHK_PCI_PID(pcr, PID_524A))  in rts5249_init_from_cfg()
100 		rtsx_pci_read_config_dword(pcr,  in rts5249_init_from_cfg()
103 		rtsx_pci_read_config_dword(pcr,  in rts5249_init_from_cfg()
107 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);  in rts5249_init_from_cfg()
110 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);  in rts5249_init_from_cfg()
113 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);  in rts5249_init_from_cfg()
116 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);  in rts5249_init_from_cfg()
121 		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);  in rts5249_init_from_cfg()
125 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);  in rts5249_init_from_cfg()
132 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)  in rts5249_init_from_hw()  argument
134 	struct rtsx_cr_option *option = &(pcr->option);  in rts5249_init_from_hw()
136 	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN  in rts5249_init_from_hw()
145 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)  in rts5249_extra_init_hw()  argument
147 	struct rtsx_cr_option *option = &(pcr->option);  in rts5249_extra_init_hw()
149 	rts5249_init_from_cfg(pcr);  in rts5249_extra_init_hw()
150 	rts5249_init_from_hw(pcr);  in rts5249_extra_init_hw()
152 	rtsx_pci_init_cmd(pcr);  in rts5249_extra_init_hw()
155 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);  in rts5249_extra_init_hw()
157 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);  in rts5249_extra_init_hw()
159 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);  in rts5249_extra_init_hw()
161 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);  in rts5249_extra_init_hw()
162 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);  in rts5249_extra_init_hw()
164 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);  in rts5249_extra_init_hw()
166 	rts5249_fill_driving(pcr, OUTPUT_3V3);  in rts5249_extra_init_hw()
167 	if (pcr->flags & PCR_REVERSE_SOCKET)  in rts5249_extra_init_hw()
168 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);  in rts5249_extra_init_hw()
170 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);  in rts5249_extra_init_hw()
177 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,  in rts5249_extra_init_hw()
180 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,  in rts5249_extra_init_hw()
183 	return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);  in rts5249_extra_init_hw()
186 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)  in rts5249_optimize_phy()  argument
190 	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);  in rts5249_optimize_phy()
194 	err = rtsx_pci_write_phy_register(pcr, PHY_REV,  in rts5249_optimize_phy()
205 	err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,  in rts5249_optimize_phy()
211 	err = rtsx_pci_write_phy_register(pcr, PHY_PCR,  in rts5249_optimize_phy()
218 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,  in rts5249_optimize_phy()
225 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,  in rts5249_optimize_phy()
232 	err = rtsx_pci_write_phy_register(pcr, PHY_RDR,  in rts5249_optimize_phy()
236 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,  in rts5249_optimize_phy()
240 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,  in rts5249_optimize_phy()
246 	return rtsx_pci_write_phy_register(pcr, PHY_TUNE,  in rts5249_optimize_phy()
252 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)  in rtsx_base_turn_on_led()  argument
254 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);  in rtsx_base_turn_on_led()
257 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)  in rtsx_base_turn_off_led()  argument
259 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);  in rtsx_base_turn_off_led()
262 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)  in rtsx_base_enable_auto_blink()  argument
264 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);  in rtsx_base_enable_auto_blink()
267 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)  in rtsx_base_disable_auto_blink()  argument
269 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);  in rtsx_base_disable_auto_blink()
272 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)  in rtsx_base_card_power_on()  argument
275 	struct rtsx_cr_option *option = &pcr->option;  in rtsx_base_card_power_on()
278 		rtsx_pci_enable_ocp(pcr);  in rtsx_base_card_power_on()
280 	rtsx_pci_init_cmd(pcr);  in rtsx_base_card_power_on()
281 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rtsx_base_card_power_on()
283 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rtsx_base_card_power_on()
285 	err = rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_card_power_on()
291 	rtsx_pci_init_cmd(pcr);  in rtsx_base_card_power_on()
292 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rtsx_base_card_power_on()
294 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rtsx_base_card_power_on()
296 	return rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_card_power_on()
299 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)  in rtsx_base_card_power_off()  argument
301 	struct rtsx_cr_option *option = &pcr->option;  in rtsx_base_card_power_off()
304 		rtsx_pci_disable_ocp(pcr);  in rtsx_base_card_power_off()
306 	rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);  in rtsx_base_card_power_off()
308 	rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);  in rtsx_base_card_power_off()
312 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)  in rtsx_base_switch_output_voltage()  argument
319 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,  in rtsx_base_switch_output_voltage()
326 		if (CHK_PCI_PID(pcr, 0x5249)) {  in rtsx_base_switch_output_voltage()
327 			err = rtsx_pci_update_phy(pcr, PHY_BACR,  in rtsx_base_switch_output_voltage()
334 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,  in rtsx_base_switch_output_voltage()
340 		pcr_dbg(pcr, "unknown output voltage %d\n", voltage);  in rtsx_base_switch_output_voltage()
345 	rtsx_pci_init_cmd(pcr);  in rtsx_base_switch_output_voltage()
346 	rts5249_fill_driving(pcr, voltage);  in rtsx_base_switch_output_voltage()
347 	return rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_switch_output_voltage()
350 static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)  in rts5249_set_aspm()  argument
352 	struct rtsx_cr_option *option = &pcr->option;  in rts5249_set_aspm()
355 	if (pcr->aspm_enabled == enable)  in rts5249_set_aspm()
360 			val = pcr->aspm_en;  in rts5249_set_aspm()
361 		rtsx_pci_update_cfg_byte(pcr,  in rts5249_set_aspm()
362 			pcr->pcie_cap + PCI_EXP_LNKCTL,  in rts5249_set_aspm()
369 		rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);  in rts5249_set_aspm()
372 	pcr->aspm_enabled = enable;  in rts5249_set_aspm()
442 void rts5249_init_params(struct rtsx_pcr *pcr)  in rts5249_init_params()  argument
444 	struct rtsx_cr_option *option = &(pcr->option);  in rts5249_init_params()
446 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;  in rts5249_init_params()
447 	pcr->num_slots = 2;  in rts5249_init_params()
448 	pcr->ops = &rts5249_pcr_ops;  in rts5249_init_params()
450 	pcr->flags = 0;  in rts5249_init_params()
451 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;  in rts5249_init_params()
452 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;  in rts5249_init_params()
453 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;  in rts5249_init_params()
454 	pcr->aspm_en = ASPM_L1_EN;  in rts5249_init_params()
455 	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);  in rts5249_init_params()
456 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);  in rts5249_init_params()
458 	pcr->ic_version = rts5249_get_ic_version(pcr);  in rts5249_init_params()
459 	pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;  in rts5249_init_params()
460 	pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;  in rts5249_init_params()
461 	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;  in rts5249_init_params()
462 	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;  in rts5249_init_params()
464 	pcr->reg_pm_ctrl3 = PM_CTRL3;  in rts5249_init_params()
481 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)  in rts524a_write_phy()  argument
485 	return __rtsx_pci_write_phy_register(pcr, addr, val);  in rts524a_write_phy()
488 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)  in rts524a_read_phy()  argument
492 	return __rtsx_pci_read_phy_register(pcr, addr, val);  in rts524a_read_phy()
495 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)  in rts524a_optimize_phy()  argument
499 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,  in rts524a_optimize_phy()
504 	rtsx_pci_write_phy_register(pcr, PHY_PCR,  in rts524a_optimize_phy()
507 	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,  in rts524a_optimize_phy()
510 	if (is_version(pcr, 0x524A, IC_VER_A)) {  in rts524a_optimize_phy()
511 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,  in rts524a_optimize_phy()
513 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,  in rts524a_optimize_phy()
516 		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,  in rts524a_optimize_phy()
519 		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,  in rts524a_optimize_phy()
521 		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,  in rts524a_optimize_phy()
531 	rtsx_pci_write_phy_register(pcr, PHY_ANA08,  in rts524a_optimize_phy()
538 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)  in rts524a_extra_init_hw()  argument
540 	rts5249_extra_init_hw(pcr);  in rts524a_extra_init_hw()
542 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,  in rts524a_extra_init_hw()
544 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);  in rts524a_extra_init_hw()
545 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,  in rts524a_extra_init_hw()
547 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);  in rts524a_extra_init_hw()
548 	if (is_version(pcr, 0x524A, IC_VER_A)) {  in rts524a_extra_init_hw()
549 		rtsx_pci_write_register(pcr, LDO_DV18_CFG,  in rts524a_extra_init_hw()
551 		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,  in rts524a_extra_init_hw()
553 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts524a_extra_init_hw()
555 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts524a_extra_init_hw()
557 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,  in rts524a_extra_init_hw()
559 		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,  in rts524a_extra_init_hw()
566 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)  in rts5250_set_l1off_cfg_sub_d0()  argument
568 	struct rtsx_cr_option *option = &(pcr->option);  in rts5250_set_l1off_cfg_sub_d0()
570 	u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);  in rts5250_set_l1off_cfg_sub_d0()
575 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);  in rts5250_set_l1off_cfg_sub_d0()
576 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);  in rts5250_set_l1off_cfg_sub_d0()
589 		if (rtsx_check_dev_flag(pcr,  in rts5250_set_l1off_cfg_sub_d0()
597 	rtsx_set_l1off_sub(pcr, val);  in rts5250_set_l1off_cfg_sub_d0()
618 void rts524a_init_params(struct rtsx_pcr *pcr)  in rts524a_init_params()  argument
620 	rts5249_init_params(pcr);  in rts524a_init_params()
621 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;  in rts524a_init_params()
622 	pcr->option.ltr_l1off_snooze_sspwrgate =  in rts524a_init_params()
625 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;  in rts524a_init_params()
626 	pcr->ops = &rts524a_pcr_ops;  in rts524a_init_params()
628 	pcr->option.ocp_en = 1;  in rts524a_init_params()
629 	if (pcr->option.ocp_en)  in rts524a_init_params()
630 		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;  in rts524a_init_params()
631 	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;  in rts524a_init_params()
632 	pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;  in rts524a_init_params()
636 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)  in rts525a_card_power_on()  argument
638 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1,  in rts525a_card_power_on()
640 	return rtsx_base_card_power_on(pcr, card);  in rts525a_card_power_on()
643 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)  in rts525a_switch_output_voltage()  argument
647 		rtsx_pci_write_register(pcr, LDO_CONFIG2,  in rts525a_switch_output_voltage()
649 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);  in rts525a_switch_output_voltage()
652 		rtsx_pci_write_register(pcr, LDO_CONFIG2,  in rts525a_switch_output_voltage()
654 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,  in rts525a_switch_output_voltage()
661 	rtsx_pci_init_cmd(pcr);  in rts525a_switch_output_voltage()
662 	rts5249_fill_driving(pcr, voltage);  in rts525a_switch_output_voltage()
663 	return rtsx_pci_send_cmd(pcr, 100);  in rts525a_switch_output_voltage()
666 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)  in rts525a_optimize_phy()  argument
670 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,  in rts525a_optimize_phy()
675 	rtsx_pci_write_phy_register(pcr, _PHY_FLD0,  in rts525a_optimize_phy()
680 	rtsx_pci_write_phy_register(pcr, _PHY_ANA03,  in rts525a_optimize_phy()
684 	if (is_version(pcr, 0x525A, IC_VER_A))  in rts525a_optimize_phy()
685 		rtsx_pci_write_phy_register(pcr, _PHY_REV0,  in rts525a_optimize_phy()
692 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)  in rts525a_extra_init_hw()  argument
694 	rts5249_extra_init_hw(pcr);  in rts525a_extra_init_hw()
696 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);  in rts525a_extra_init_hw()
697 	if (is_version(pcr, 0x525A, IC_VER_A)) {  in rts525a_extra_init_hw()
698 		rtsx_pci_write_register(pcr, L1SUB_CONFIG2,  in rts525a_extra_init_hw()
700 		rtsx_pci_write_register(pcr, RREF_CFG,  in rts525a_extra_init_hw()
702 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts525a_extra_init_hw()
704 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,  in rts525a_extra_init_hw()
706 		rtsx_pci_write_register(pcr, LDO_AV12S_CFG,  in rts525a_extra_init_hw()
708 		rtsx_pci_write_register(pcr, LDO_VCC_CFG0,  in rts525a_extra_init_hw()
710 		rtsx_pci_write_register(pcr, OOBS_CONFIG,  in rts525a_extra_init_hw()
733 void rts525a_init_params(struct rtsx_pcr *pcr)  in rts525a_init_params()  argument
735 	rts5249_init_params(pcr);  in rts525a_init_params()
736 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;  in rts525a_init_params()
737 	pcr->option.ltr_l1off_snooze_sspwrgate =  in rts525a_init_params()
740 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;  in rts525a_init_params()
741 	pcr->ops = &rts525a_pcr_ops;  in rts525a_init_params()
743 	pcr->option.ocp_en = 1;  in rts525a_init_params()
744 	if (pcr->option.ocp_en)  in rts525a_init_params()
745 		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;  in rts525a_init_params()
746 	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;  in rts525a_init_params()
747 	pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;  in rts525a_init_params()