226 #define MBOX_BIT BIT  macro
227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
789 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in db8500_prcmu_set_power_state()
798 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_power_state()
832 		while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in config_wakeups()
837 		writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in config_wakeups()
902 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_arm_opp()
909 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_arm_opp()
1009 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_ape_opp()
1017 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_ape_opp()
1074 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_request_ape_opp_100_voltage()
1079 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_request_ape_opp_100_voltage()
1103 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in prcmu_release_usb_wakeup_state()
1109 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in prcmu_release_usb_wakeup_state()
1134 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in request_pll()
1140 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in request_pll()
1186 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))  in db8500_prcmu_set_epod()
1196 	writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_epod()
1283 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))  in request_sysclk()
1289 	writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);  in request_sysclk()
2002 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_esram0_deep_sleep()
2012 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_esram0_deep_sleep()
2024 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotdog()
2030 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotdog()
2042 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotmon()
2051 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotmon()
2064 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in config_hot_period()
2070 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in config_hot_period()
2098 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in prcmu_a9wdog()
2108 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in prcmu_a9wdog()
2181 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_read()
2190 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_read()
2231 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_write_masked()
2240 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_write_masked()
2377 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_modem_reset()
2381 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_modem_reset()
2398 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in ack_dbb_wakeup()
2402 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in ack_dbb_wakeup()
2447 	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);  in read_mailbox_0()
2460 	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);  in read_mailbox_1()
2468 	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);  in read_mailbox_2()
2475 	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);  in read_mailbox_3()
2502 	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);  in read_mailbox_4()
2514 	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);  in read_mailbox_5()
2521 	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);  in read_mailbox_6()
2527 	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);  in read_mailbox_7()
2554 		if (bits & MBOX_BIT(n)) {  in prcmu_irq_handler()
2555 			bits -= MBOX_BIT(n);  in prcmu_irq_handler()