Lines Matching refs:TEGRA210_MC_RESET
1080 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ macro
1090 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1091 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1092 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1093 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1094 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1095 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1096 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1097 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1098 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1099 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1101 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1102 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1103 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1104 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1105 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1106 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1107 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1108 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1109 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1110 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1111 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1112 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1113 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1114 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1115 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1116 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1117 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1118 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1119 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),