Lines Matching refs:timing
539 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
544 timing = &emc->timings[i]; in tegra_emc_find_timing()
549 if (!timing) { in tegra_emc_find_timing()
554 return timing; in tegra_emc_find_timing()
560 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
568 if (!timing) in tegra_emc_prepare_timing_change()
571 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
573 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
605 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
625 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
631 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
650 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
652 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
658 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
659 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
662 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
663 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
665 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
667 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
671 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
672 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
675 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
676 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
679 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
680 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
690 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
694 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
700 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
708 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
714 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
737 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
738 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
739 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
740 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
742 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
744 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
754 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
755 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
756 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
757 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
758 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
759 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
763 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
773 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
774 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
788 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change() local
792 if (!timing) in tegra_emc_complete_timing_change()
799 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
800 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
804 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
805 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
808 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
812 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
814 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
821 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
822 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
826 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
834 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
837 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
843 struct emc_timing *timing) in emc_read_current_timing() argument
848 timing->emc_burst_data[i] = in emc_read_current_timing()
851 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
853 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
854 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
855 timing->emc_mode_1 = 0; in emc_read_current_timing()
856 timing->emc_mode_2 = 0; in emc_read_current_timing()
857 timing->emc_mode_4 = 0; in emc_read_current_timing()
858 timing->emc_mode_reset = 0; in emc_read_current_timing()
875 struct emc_timing *timing, in load_one_timing_from_dt() argument
888 timing->rate = value; in load_one_timing_from_dt()
891 timing->emc_burst_data, in load_one_timing_from_dt()
892 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
901 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
950 struct emc_timing *timing; in tegra_emc_load_timings_from_dt() local
954 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
962 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
964 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
971 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
1029 struct emc_timing *timing = &emc->timings[i]; in emc_debug_supported_rates_show() local
1031 seq_printf(s, "%s%lu", prefix, timing->rate); in emc_debug_supported_rates_show()