Lines Matching refs:mc_readl
85 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
96 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
107 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
118 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
288 value = mc_readl(mc, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
298 value = mc_readl(mc, la->reg); in tegra_mc_setup_latency_allowance()
336 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); in tegra_mc_get_emem_device_count()
461 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra_mc_irq()
475 value = mc_readl(mc, MC_ERR_STATUS); in tegra_mc_irq()
537 value = mc_readl(mc, MC_ERR_ADR); in tegra_mc_irq()
558 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_irq()
573 value = mc_readl(mc, reg); in tegra20_mc_irq()
584 value = mc_readl(mc, reg); in tegra20_mc_irq()
595 value = mc_readl(mc, reg); in tegra20_mc_irq()
611 addr = mc_readl(mc, reg + sizeof(u32)); in tegra20_mc_irq()