Lines Matching refs:mc
77 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument
83 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
85 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
86 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
88 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_block_dma_common()
93 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, in tegra_mc_dma_idling_common() argument
96 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
99 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, in tegra_mc_unblock_dma_common() argument
105 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_unblock_dma_common()
107 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
108 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
110 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_unblock_dma_common()
115 static int tegra_mc_reset_status_common(struct tegra_mc *mc, in tegra_mc_reset_status_common() argument
118 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
133 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, in tegra_mc_reset_find() argument
138 for (i = 0; i < mc->soc->num_resets; i++) in tegra_mc_reset_find()
139 if (mc->soc->resets[i].id == id) in tegra_mc_reset_find()
140 return &mc->soc->resets[i]; in tegra_mc_reset_find()
148 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_assert() local
154 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_assert()
158 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_assert()
164 err = rst_ops->block_dma(mc, rst); in tegra_mc_hotreset_assert()
166 dev_err(mc->dev, "failed to block %s DMA: %d\n", in tegra_mc_hotreset_assert()
174 while (!rst_ops->dma_idling(mc, rst)) { in tegra_mc_hotreset_assert()
176 dev_err(mc->dev, "failed to flush %s DMA\n", in tegra_mc_hotreset_assert()
187 err = rst_ops->hotreset_assert(mc, rst); in tegra_mc_hotreset_assert()
189 dev_err(mc->dev, "failed to hot reset %s: %d\n", in tegra_mc_hotreset_assert()
201 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_deassert() local
206 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_deassert()
210 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_deassert()
216 err = rst_ops->hotreset_deassert(mc, rst); in tegra_mc_hotreset_deassert()
218 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", in tegra_mc_hotreset_deassert()
226 err = rst_ops->unblock_dma(mc, rst); in tegra_mc_hotreset_deassert()
228 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", in tegra_mc_hotreset_deassert()
240 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_status() local
244 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_status()
248 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_status()
252 return rst_ops->reset_status(mc, rst); in tegra_mc_hotreset_status()
261 static int tegra_mc_reset_setup(struct tegra_mc *mc) in tegra_mc_reset_setup() argument
265 mc->reset.ops = &tegra_mc_reset_ops; in tegra_mc_reset_setup()
266 mc->reset.owner = THIS_MODULE; in tegra_mc_reset_setup()
267 mc->reset.of_node = mc->dev->of_node; in tegra_mc_reset_setup()
268 mc->reset.of_reset_n_cells = 1; in tegra_mc_reset_setup()
269 mc->reset.nr_resets = mc->soc->num_resets; in tegra_mc_reset_setup()
271 err = reset_controller_register(&mc->reset); in tegra_mc_reset_setup()
278 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) in tegra_mc_setup_latency_allowance() argument
285 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); in tegra_mc_setup_latency_allowance()
288 value = mc_readl(mc, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
291 mc_writel(mc, value, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
294 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_setup_latency_allowance()
295 const struct tegra_mc_la *la = &mc->soc->clients[i].la; in tegra_mc_setup_latency_allowance()
298 value = mc_readl(mc, la->reg); in tegra_mc_setup_latency_allowance()
301 mc_writel(mc, value, la->reg); in tegra_mc_setup_latency_allowance()
305 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in tegra_mc_setup_latency_allowance()
310 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) in tegra_mc_write_emem_configuration() argument
315 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
316 if (mc->timings[i].rate == rate) { in tegra_mc_write_emem_configuration()
317 timing = &mc->timings[i]; in tegra_mc_write_emem_configuration()
323 dev_err(mc->dev, "no memory timing registered for rate %lu\n", in tegra_mc_write_emem_configuration()
328 for (i = 0; i < mc->soc->num_emem_regs; ++i) in tegra_mc_write_emem_configuration()
329 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
332 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) in tegra_mc_get_emem_device_count() argument
336 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); in tegra_mc_get_emem_device_count()
343 static int load_one_timing(struct tegra_mc *mc, in load_one_timing() argument
352 dev_err(mc->dev, in load_one_timing()
358 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, in load_one_timing()
365 mc->soc->num_emem_regs); in load_one_timing()
367 dev_err(mc->dev, in load_one_timing()
376 static int load_timings(struct tegra_mc *mc, struct device_node *node) in load_timings() argument
383 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), in load_timings()
385 if (!mc->timings) in load_timings()
388 mc->num_timings = child_count; in load_timings()
391 timing = &mc->timings[i++]; in load_timings()
393 err = load_one_timing(mc, timing, child); in load_timings()
403 static int tegra_mc_setup_timings(struct tegra_mc *mc) in tegra_mc_setup_timings() argument
411 mc->num_timings = 0; in tegra_mc_setup_timings()
413 for_each_child_of_node(mc->dev->of_node, node) { in tegra_mc_setup_timings()
419 err = load_timings(mc, node); in tegra_mc_setup_timings()
426 if (mc->num_timings == 0) in tegra_mc_setup_timings()
427 dev_warn(mc->dev, in tegra_mc_setup_timings()
456 struct tegra_mc *mc = data; in tegra_mc_irq() local
461 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra_mc_irq()
475 value = mc_readl(mc, MC_ERR_STATUS); in tegra_mc_irq()
478 if (mc->soc->num_address_bits > 32) { in tegra_mc_irq()
495 id = value & mc->soc->client_id_mask; in tegra_mc_irq()
497 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_irq()
498 if (mc->soc->clients[i].id == id) { in tegra_mc_irq()
499 client = mc->soc->clients[i].name; in tegra_mc_irq()
537 value = mc_readl(mc, MC_ERR_ADR); in tegra_mc_irq()
540 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", in tegra_mc_irq()
546 mc_writel(mc, status, MC_INTSTATUS); in tegra_mc_irq()
553 struct tegra_mc *mc = data; in tegra20_mc_irq() local
558 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_irq()
573 value = mc_readl(mc, reg); in tegra20_mc_irq()
575 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
584 value = mc_readl(mc, reg); in tegra20_mc_irq()
586 id = (value >> 1) & mc->soc->client_id_mask; in tegra20_mc_irq()
595 value = mc_readl(mc, reg); in tegra20_mc_irq()
597 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
610 client = mc->soc->clients[id].name; in tegra20_mc_irq()
611 addr = mc_readl(mc, reg + sizeof(u32)); in tegra20_mc_irq()
613 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", in tegra20_mc_irq()
619 mc_writel(mc, status, MC_INTSTATUS); in tegra20_mc_irq()
627 struct tegra_mc *mc; in tegra_mc_probe() local
631 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); in tegra_mc_probe()
632 if (!mc) in tegra_mc_probe()
635 platform_set_drvdata(pdev, mc); in tegra_mc_probe()
636 spin_lock_init(&mc->lock); in tegra_mc_probe()
637 mc->soc = of_device_get_match_data(&pdev->dev); in tegra_mc_probe()
638 mc->dev = &pdev->dev; in tegra_mc_probe()
641 mc->tick = 30; in tegra_mc_probe()
644 mc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_mc_probe()
645 if (IS_ERR(mc->regs)) in tegra_mc_probe()
646 return PTR_ERR(mc->regs); in tegra_mc_probe()
648 mc->clk = devm_clk_get(&pdev->dev, "mc"); in tegra_mc_probe()
649 if (IS_ERR(mc->clk)) { in tegra_mc_probe()
651 PTR_ERR(mc->clk)); in tegra_mc_probe()
652 return PTR_ERR(mc->clk); in tegra_mc_probe()
656 if (mc->soc == &tegra20_mc_soc) { in tegra_mc_probe()
661 err = tegra_mc_setup_latency_allowance(mc); in tegra_mc_probe()
671 err = tegra_mc_setup_timings(mc); in tegra_mc_probe()
679 mc->irq = platform_get_irq(pdev, 0); in tegra_mc_probe()
680 if (mc->irq < 0) { in tegra_mc_probe()
682 return mc->irq; in tegra_mc_probe()
685 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); in tegra_mc_probe()
687 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
689 err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, in tegra_mc_probe()
690 dev_name(&pdev->dev), mc); in tegra_mc_probe()
692 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, in tegra_mc_probe()
697 err = tegra_mc_reset_setup(mc); in tegra_mc_probe()
702 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { in tegra_mc_probe()
703 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); in tegra_mc_probe()
704 if (IS_ERR(mc->smmu)) { in tegra_mc_probe()
706 PTR_ERR(mc->smmu)); in tegra_mc_probe()
707 mc->smmu = NULL; in tegra_mc_probe()
711 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { in tegra_mc_probe()
712 mc->gart = tegra_gart_probe(&pdev->dev, mc); in tegra_mc_probe()
713 if (IS_ERR(mc->gart)) { in tegra_mc_probe()
715 PTR_ERR(mc->gart)); in tegra_mc_probe()
716 mc->gart = NULL; in tegra_mc_probe()
725 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_suspend() local
728 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { in tegra_mc_suspend()
729 err = tegra_gart_suspend(mc->gart); in tegra_mc_suspend()
739 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_resume() local
742 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { in tegra_mc_resume()
743 err = tegra_gart_resume(mc->gart); in tegra_mc_resume()