Lines Matching refs:tim1
435 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw() local
438 tim1 |= val << T_WTR_SHIFT; in get_sdram_tim_1_shdw()
444 tim1 |= (val - 1) << T_RRD_SHIFT; in get_sdram_tim_1_shdw()
447 tim1 |= val << T_RC_SHIFT; in get_sdram_tim_1_shdw()
450 tim1 |= (val - 1) << T_RAS_SHIFT; in get_sdram_tim_1_shdw()
453 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw()
456 tim1 |= val << T_RCD_SHIFT; in get_sdram_tim_1_shdw()
459 tim1 |= val << T_RP_SHIFT; in get_sdram_tim_1_shdw()
461 return tim1; in get_sdram_tim_1_shdw()
468 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw_derated() local
471 tim1 = val << T_WTR_SHIFT; in get_sdram_tim_1_shdw_derated()
483 tim1 |= val << T_RRD_SHIFT; in get_sdram_tim_1_shdw_derated()
486 tim1 |= (val - 1) << T_RC_SHIFT; in get_sdram_tim_1_shdw_derated()
490 tim1 |= val << T_RAS_SHIFT; in get_sdram_tim_1_shdw_derated()
493 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw_derated()
496 tim1 |= (val - 1) << T_RCD_SHIFT; in get_sdram_tim_1_shdw_derated()
499 tim1 |= (val - 1) << T_RP_SHIFT; in get_sdram_tim_1_shdw_derated()
501 return tim1; in get_sdram_tim_1_shdw_derated()
922 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local
928 tim1 = regs->sdram_tim1_shdw; in setup_temperature_sensitive_regs()
940 tim1 = regs->sdram_tim1_shdw_derated; in setup_temperature_sensitive_regs()
946 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); in setup_temperature_sensitive_regs()