75 static u32		t_ck; /* DDR clock period in ps */  variable
219 	t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);  in set_ddr_clk_period()
437 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;  in get_sdram_tim_1_shdw()
441 		val = DIV_ROUND_UP(timings->tFAW, t_ck*4);  in get_sdram_tim_1_shdw()
443 		val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));  in get_sdram_tim_1_shdw()
446 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;  in get_sdram_tim_1_shdw()
449 	val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));  in get_sdram_tim_1_shdw()
452 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;  in get_sdram_tim_1_shdw()
455 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;  in get_sdram_tim_1_shdw()
458 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;  in get_sdram_tim_1_shdw()
470 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;  in get_sdram_tim_1_shdw_derated()
478 		val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;  in get_sdram_tim_1_shdw_derated()
480 		val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);  in get_sdram_tim_1_shdw_derated()
485 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);  in get_sdram_tim_1_shdw_derated()
488 	val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);  in get_sdram_tim_1_shdw_derated()
492 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;  in get_sdram_tim_1_shdw_derated()
495 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));  in get_sdram_tim_1_shdw_derated()
498 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));  in get_sdram_tim_1_shdw_derated()
514 	val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;  in get_sdram_tim_2_shdw()
518 	val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;  in get_sdram_tim_2_shdw()
524 	val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;  in get_sdram_tim_2_shdw()
541 	val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;  in get_sdram_tim_3_shdw()
547 		val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;  in get_sdram_tim_3_shdw()
549 		val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;  in get_sdram_tim_3_shdw()
553 	val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;  in get_sdram_tim_3_shdw()
556 	val = DIV_ROUND_UP(timings->tCKESR, t_ck);  in get_sdram_tim_3_shdw()
643 		val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;  in get_read_idle_ctrl_shdw()
662 		val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;  in get_dll_calib_ctrl_shdw()
677 	val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;  in get_ddr_phy_ctrl_1_attilaphy_4d()
707 			t_ck) - 1) << READ_LATENCY_SHIFT_4D5);  in get_phy_ctrl_1_intelliphy_4d5()
717 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);  in get_ext_phy_ctrl_2_intelliphy_4d5()
728 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);  in get_ext_phy_ctrl_3_intelliphy_4d5()
739 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);  in get_ext_phy_ctrl_4_intelliphy_4d5()