83 	set_field(&val, field, mask); \
353 static inline void set_field(u32 *valp, u32 field, u32 mask)  in set_field()  function
399 		set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);  in camerarx_phy_enable()
400 		set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK);  in camerarx_phy_enable()
402 		set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK);  in camerarx_phy_enable()
403 		set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK);  in camerarx_phy_enable()
405 		set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);  in camerarx_phy_enable()
406 		set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK);  in camerarx_phy_enable()
408 		set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK);  in camerarx_phy_enable()
409 		set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK);  in camerarx_phy_enable()
425 		set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);  in camerarx_phy_disable()
427 		set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);  in camerarx_phy_disable()
560 	set_field(&val, CAL_GEN_ENABLE,  in csi2_init()
562 	set_field(&val, CAL_GEN_ENABLE,  in csi2_init()
564 	set_field(&val, CAL_GEN_DISABLE,  in csi2_init()
566 	set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);  in csi2_init()
572 	set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,  in csi2_init()
574 	set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON,  in csi2_init()
589 	set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK);  in csi2_init()
590 	set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK);  in csi2_init()
591 	set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,  in csi2_init()
593 	set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK);  in csi2_init()
594 	set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK);  in csi2_init()
608 	set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);  in csi2_lane_config()
609 	set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);  in csi2_lane_config()
617 		set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);  in csi2_lane_config()
618 		set_field(&val, mipi_csi2->lane_polarities[lane + 1],  in csi2_lane_config()
644 	set_field(&val, ctx->csi2_port, CAL_CSI2_CTX_CPORT_MASK);  in csi2_ctx_config()
653 	set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK);  in csi2_ctx_config()
655 	set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK);  in csi2_ctx_config()
657 	set_field(&val, 0, CAL_CSI2_CTX_LINES_MASK);  in csi2_ctx_config()
658 	set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);  in csi2_ctx_config()
659 	set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,  in csi2_ctx_config()
671 	set_field(&val, CAL_PIX_PROC_EXTRACT_B8, CAL_PIX_PROC_EXTRACT_MASK);  in pix_proc_config()
672 	set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);  in pix_proc_config()
673 	set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);  in pix_proc_config()
674 	set_field(&val, CAL_PIX_PROC_PACK_B8, CAL_PIX_PROC_PACK_MASK);  in pix_proc_config()
675 	set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK);  in pix_proc_config()
676 	set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK);  in pix_proc_config()
688 	set_field(&val, ctx->csi2_port, CAL_WR_DMA_CTRL_CPORT_MASK);  in cal_wr_dma_config()
689 	set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,  in cal_wr_dma_config()
691 	set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,  in cal_wr_dma_config()
693 	set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,  in cal_wr_dma_config()
695 	set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK);  in cal_wr_dma_config()
713 	set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);  in cal_wr_dma_config()
719 	set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK);  in cal_wr_dma_config()
774 	set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,  in csi2_phy_config()
776 	set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);  in csi2_phy_config()
777 	set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);  in csi2_phy_config()
783 	set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);  in csi2_phy_config()
784 	set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);  in csi2_phy_config()
785 	set_field(&reg1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);  in csi2_phy_config()
786 	set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);  in csi2_phy_config()