Lines Matching refs:vfe
395 u8 vfe, u8 enable) in ispif_select_clk_mux() argument
402 val &= ~(0xf << (vfe * 8)); in ispif_select_clk_mux()
404 val |= (csid << (vfe * 8)); in ispif_select_clk_mux()
410 val &= ~(0xf << (vfe * 12)); in ispif_select_clk_mux()
412 val |= (csid << (vfe * 12)); in ispif_select_clk_mux()
418 val &= ~(0xf << (4 + (vfe * 8))); in ispif_select_clk_mux()
420 val |= (csid << (4 + (vfe * 8))); in ispif_select_clk_mux()
426 val &= ~(0xf << (4 + (vfe * 12))); in ispif_select_clk_mux()
428 val |= (csid << (4 + (vfe * 12))); in ispif_select_clk_mux()
434 val &= ~(0xf << (8 + (vfe * 12))); in ispif_select_clk_mux()
436 val |= (csid << (8 + (vfe * 12))); in ispif_select_clk_mux()
453 enum ispif_intf intf, u8 vfe) in ispif_validate_intf_status() argument
461 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0)); in ispif_validate_intf_status()
465 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0)); in ispif_validate_intf_status()
469 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1)); in ispif_validate_intf_status()
473 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1)); in ispif_validate_intf_status()
477 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2)); in ispif_validate_intf_status()
499 enum ispif_intf intf, u8 vfe) in ispif_wait_for_stop() argument
507 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0); in ispif_wait_for_stop()
510 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0); in ispif_wait_for_stop()
513 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1); in ispif_wait_for_stop()
516 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1); in ispif_wait_for_stop()
519 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2); in ispif_wait_for_stop()
544 u8 csid, u8 vfe, u8 enable) in ispif_select_csid() argument
548 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); in ispif_select_csid()
577 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); in ispif_select_csid()
589 u8 cid, u8 vfe, u8 enable) in ispif_select_cid() argument
597 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0); in ispif_select_cid()
600 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0); in ispif_select_cid()
603 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1); in ispif_select_cid()
606 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1); in ispif_select_cid()
609 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2); in ispif_select_cid()
630 u8 vfe, u8 enable) in ispif_config_irq() argument
636 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
640 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
642 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); in ispif_config_irq()
645 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
649 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); in ispif_config_irq()
651 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); in ispif_config_irq()
654 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
658 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
660 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); in ispif_config_irq()
663 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
667 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); in ispif_config_irq()
669 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); in ispif_config_irq()
672 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); in ispif_config_irq()
676 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); in ispif_config_irq()
678 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe)); in ispif_config_irq()
695 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable) in ispif_config_pack() argument
706 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0); in ispif_config_pack()
708 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0); in ispif_config_pack()
712 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1); in ispif_config_pack()
714 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1); in ispif_config_pack()
718 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2); in ispif_config_pack()
720 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2); in ispif_config_pack()
743 enum ispif_intf intf, u8 vfe, u8 vc) in ispif_set_intf_cmd() argument
748 val = &ispif->intf_cmd[vfe].cmd_1; in ispif_set_intf_cmd()
752 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); in ispif_set_intf_cmd()
755 val = &ispif->intf_cmd[vfe].cmd_0; in ispif_set_intf_cmd()
759 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); in ispif_set_intf_cmd()
779 u8 vfe = line->vfe_id; in ispif_set_stream() local
791 ispif_select_clk_mux(ispif, intf, csid, vfe, 1); in ispif_set_stream()
793 ret = ispif_validate_intf_status(ispif, intf, vfe); in ispif_set_stream()
799 ispif_select_csid(ispif, intf, csid, vfe, 1); in ispif_set_stream()
800 ispif_select_cid(ispif, intf, cid, vfe, 1); in ispif_set_stream()
801 ispif_config_irq(ispif, intf, vfe, 1); in ispif_set_stream()
805 intf, cid, vfe, 1); in ispif_set_stream()
807 intf, vfe, vc); in ispif_set_stream()
811 intf, vfe, vc); in ispif_set_stream()
814 ret = ispif_wait_for_stop(ispif, intf, vfe); in ispif_set_stream()
822 intf, cid, vfe, 0); in ispif_set_stream()
823 ispif_config_irq(ispif, intf, vfe, 0); in ispif_set_stream()
824 ispif_select_cid(ispif, intf, cid, vfe, 0); in ispif_set_stream()
825 ispif_select_csid(ispif, intf, csid, vfe, 0); in ispif_set_stream()
826 ispif_select_clk_mux(ispif, intf, csid, vfe, 0); in ispif_set_stream()