25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
29 static int set_qam_standard(struct drxk_state *state,
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
33 static int set_dvbt_standard(struct drxk_state *state,
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state)  in is_dvbt()  argument
45 	return state->m_operation_mode == OM_DVBT;  in is_dvbt()
48 static bool is_qam(struct drxk_state *state)  in is_qam()  argument
50 	return state->m_operation_mode == OM_QAM_ITU_A ||  in is_qam()
51 	    state->m_operation_mode == OM_QAM_ITU_B ||  in is_qam()
52 	    state->m_operation_mode == OM_QAM_ITU_C;  in is_qam()
94 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
97 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
100 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
202 static int drxk_i2c_lock(struct drxk_state *state)  in drxk_i2c_lock()  argument
204 	i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);  in drxk_i2c_lock()
205 	state->drxk_i2c_exclusive_lock = true;  in drxk_i2c_lock()
210 static void drxk_i2c_unlock(struct drxk_state *state)  in drxk_i2c_unlock()  argument
212 	if (!state->drxk_i2c_exclusive_lock)  in drxk_i2c_unlock()
215 	i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);  in drxk_i2c_unlock()
216 	state->drxk_i2c_exclusive_lock = false;  in drxk_i2c_unlock()
219 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,  in drxk_i2c_transfer()  argument
222 	if (state->drxk_i2c_exclusive_lock)  in drxk_i2c_transfer()
223 		return __i2c_transfer(state->i2c, msgs, len);  in drxk_i2c_transfer()
225 		return i2c_transfer(state->i2c, msgs, len);  in drxk_i2c_transfer()
228 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)  in i2c_read1()  argument
234 	return drxk_i2c_transfer(state, msgs, 1);  in i2c_read1()
237 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)  in i2c_write()  argument
250 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
260 static int i2c_read(struct drxk_state *state,  in i2c_read()  argument
271 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
294 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)  in read16_flags()  argument
297 	u8 adr = state->demod_address, mm1[4], mm2[2], len;  in read16_flags()
299 	if (state->single_master)  in read16_flags()
314 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
323 static int read16(struct drxk_state *state, u32 reg, u16 *data)  in read16()  argument
325 	return read16_flags(state, reg, data, 0);  in read16()
328 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)  in read32_flags()  argument
331 	u8 adr = state->demod_address, mm1[4], mm2[4], len;  in read32_flags()
333 	if (state->single_master)  in read32_flags()
348 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
358 static int read32(struct drxk_state *state, u32 reg, u32 *data)  in read32()  argument
360 	return read32_flags(state, reg, data, 0);  in read32()
363 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)  in write16_flags()  argument
365 	u8 adr = state->demod_address, mm[6], len;  in write16_flags()
367 	if (state->single_master)  in write16_flags()
384 	return i2c_write(state, adr, mm, len + 2);  in write16_flags()
387 static int write16(struct drxk_state *state, u32 reg, u16 data)  in write16()  argument
389 	return write16_flags(state, reg, data, 0);  in write16()
392 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)  in write32_flags()  argument
394 	u8 adr = state->demod_address, mm[8], len;  in write32_flags()
396 	if (state->single_master)  in write32_flags()
415 	return i2c_write(state, adr, mm, len + 4);  in write32_flags()
418 static int write32(struct drxk_state *state, u32 reg, u32 data)  in write32()  argument
420 	return write32_flags(state, reg, data, 0);  in write32()
423 static int write_block(struct drxk_state *state, u32 address,  in write_block()  argument
429 	if (state->single_master)  in write_block()
433 		int chunk = blk_size > state->m_chunk_size ?  in write_block()
434 		    state->m_chunk_size : blk_size;  in write_block()
435 		u8 *adr_buf = &state->chunk[0];  in write_block()
445 			if (chunk == state->m_chunk_size)  in write_block()
453 		memcpy(&state->chunk[adr_length], p_block, chunk);  in write_block()
462 		status = i2c_write(state, state->demod_address,  in write_block()
463 				   &state->chunk[0], chunk + adr_length);  in write_block()
480 static int power_up_device(struct drxk_state *state)  in power_up_device()  argument
488 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
492 			status = i2c_write(state, state->demod_address,  in power_up_device()
498 			status = i2c_read1(state, state->demod_address,  in power_up_device()
507 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
510 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
514 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
518 	state->m_current_power_mode = DRX_POWER_UP;  in power_up_device()
528 static int init_state(struct drxk_state *state)  in init_state()  argument
584 	state->m_has_lna = false;  in init_state()
585 	state->m_has_dvbt = false;  in init_state()
586 	state->m_has_dvbc = false;  in init_state()
587 	state->m_has_atv = false;  in init_state()
588 	state->m_has_oob = false;  in init_state()
589 	state->m_has_audio = false;  in init_state()
591 	if (!state->m_chunk_size)  in init_state()
592 		state->m_chunk_size = 124;  in init_state()
594 	state->m_osc_clock_freq = 0;  in init_state()
595 	state->m_smart_ant_inverted = false;  in init_state()
596 	state->m_b_p_down_open_bridge = false;  in init_state()
599 	state->m_sys_clock_freq = 151875;  in init_state()
602 	state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *  in init_state()
605 	if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)  in init_state()
606 		state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;  in init_state()
607 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);  in init_state()
609 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;  in init_state()
611 	state->m_b_power_down = (ul_power_down != 0);  in init_state()
613 	state->m_drxk_a3_patch_code = false;  in init_state()
617 	state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;  in init_state()
618 	state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;  in init_state()
619 	state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;  in init_state()
620 	state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;  in init_state()
621 	state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;  in init_state()
622 	state->m_vsb_pga_cfg = 140;  in init_state()
625 	state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;  in init_state()
626 	state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;  in init_state()
627 	state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;  in init_state()
628 	state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;  in init_state()
629 	state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;  in init_state()
630 	state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;  in init_state()
631 	state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;  in init_state()
632 	state->m_vsb_pre_saw_cfg.reference = 0x07;  in init_state()
633 	state->m_vsb_pre_saw_cfg.use_pre_saw = true;  in init_state()
635 	state->m_Quality83percent = DEFAULT_MER_83;  in init_state()
636 	state->m_Quality93percent = DEFAULT_MER_93;  in init_state()
638 		state->m_Quality83percent = ulQual83;  in init_state()
639 		state->m_Quality93percent = ulQual93;  in init_state()
643 	state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;  in init_state()
644 	state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;  in init_state()
645 	state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;  in init_state()
646 	state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;  in init_state()
647 	state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;  in init_state()
650 	state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;  in init_state()
651 	state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;  in init_state()
652 	state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;  in init_state()
653 	state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;  in init_state()
654 	state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;  in init_state()
655 	state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;  in init_state()
656 	state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;  in init_state()
657 	state->m_atv_pre_saw_cfg.reference = 0x04;  in init_state()
658 	state->m_atv_pre_saw_cfg.use_pre_saw = true;  in init_state()
662 	state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;  in init_state()
663 	state->m_dvbt_rf_agc_cfg.output_level = 0;  in init_state()
664 	state->m_dvbt_rf_agc_cfg.min_output_level = 0;  in init_state()
665 	state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;  in init_state()
666 	state->m_dvbt_rf_agc_cfg.top = 0x2100;  in init_state()
667 	state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;  in init_state()
668 	state->m_dvbt_rf_agc_cfg.speed = 1;  in init_state()
672 	state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;  in init_state()
673 	state->m_dvbt_if_agc_cfg.output_level = 0;  in init_state()
674 	state->m_dvbt_if_agc_cfg.min_output_level = 0;  in init_state()
675 	state->m_dvbt_if_agc_cfg.max_output_level = 9000;  in init_state()
676 	state->m_dvbt_if_agc_cfg.top = 13424;  in init_state()
677 	state->m_dvbt_if_agc_cfg.cut_off_current = 0;  in init_state()
678 	state->m_dvbt_if_agc_cfg.speed = 3;  in init_state()
679 	state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;  in init_state()
680 	state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;  in init_state()
681 	/* state->m_dvbtPgaCfg = 140; */  in init_state()
683 	state->m_dvbt_pre_saw_cfg.reference = 4;  in init_state()
684 	state->m_dvbt_pre_saw_cfg.use_pre_saw = false;  in init_state()
687 	state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;  in init_state()
688 	state->m_qam_rf_agc_cfg.output_level = 0;  in init_state()
689 	state->m_qam_rf_agc_cfg.min_output_level = 6023;  in init_state()
690 	state->m_qam_rf_agc_cfg.max_output_level = 27000;  in init_state()
691 	state->m_qam_rf_agc_cfg.top = 0x2380;  in init_state()
692 	state->m_qam_rf_agc_cfg.cut_off_current = 4000;  in init_state()
693 	state->m_qam_rf_agc_cfg.speed = 3;  in init_state()
696 	state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;  in init_state()
697 	state->m_qam_if_agc_cfg.output_level = 0;  in init_state()
698 	state->m_qam_if_agc_cfg.min_output_level = 0;  in init_state()
699 	state->m_qam_if_agc_cfg.max_output_level = 9000;  in init_state()
700 	state->m_qam_if_agc_cfg.top = 0x0511;  in init_state()
701 	state->m_qam_if_agc_cfg.cut_off_current = 0;  in init_state()
702 	state->m_qam_if_agc_cfg.speed = 3;  in init_state()
703 	state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;  in init_state()
704 	state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;  in init_state()
706 	state->m_qam_pga_cfg = 140;  in init_state()
707 	state->m_qam_pre_saw_cfg.reference = 4;  in init_state()
708 	state->m_qam_pre_saw_cfg.use_pre_saw = false;  in init_state()
710 	state->m_operation_mode = OM_NONE;  in init_state()
711 	state->m_drxk_state = DRXK_UNINITIALIZED;  in init_state()
714 	state->m_enable_mpeg_output = true;	/* If TRUE; enable MPEG output */  in init_state()
715 	state->m_insert_rs_byte = false;	/* If TRUE; insert RS byte */  in init_state()
716 	state->m_invert_data = false;	/* If TRUE; invert DATA signals */  in init_state()
717 	state->m_invert_err = false;	/* If TRUE; invert ERR signal */  in init_state()
718 	state->m_invert_str = false;	/* If TRUE; invert STR signals */  in init_state()
719 	state->m_invert_val = false;	/* If TRUE; invert VAL signals */  in init_state()
720 	state->m_invert_clk = (ul_invert_ts_clock != 0);	/* If TRUE; invert CLK signals */  in init_state()
725 	state->m_dvbt_bitrate = ul_dvbt_bitrate;  in init_state()
726 	state->m_dvbc_bitrate = ul_dvbc_bitrate;  in init_state()
728 	state->m_ts_data_strength = (ul_ts_data_strength & 0x07);  in init_state()
731 	state->m_mpeg_ts_static_bitrate = 19392658;  in init_state()
732 	state->m_disable_te_ihandling = false;  in init_state()
735 		state->m_insert_rs_byte = true;  in init_state()
737 	state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;  in init_state()
739 		state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;  in init_state()
740 	state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;  in init_state()
742 		state->m_demod_lock_time_out = ul_demod_lock_time_out;  in init_state()
745 	state->m_constellation = DRX_CONSTELLATION_AUTO;  in init_state()
746 	state->m_qam_interleave_mode = DRXK_QAM_I12_J17;  in init_state()
747 	state->m_fec_rs_plen = 204 * 8;	/* fecRsPlen  annex A */  in init_state()
748 	state->m_fec_rs_prescale = 1;  in init_state()
750 	state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;  in init_state()
751 	state->m_agcfast_clip_ctrl_delay = 0;  in init_state()
753 	state->m_gpio_cfg = ul_gpio_cfg;  in init_state()
755 	state->m_b_power_down = false;  in init_state()
756 	state->m_current_power_mode = DRX_POWER_DOWN;  in init_state()
758 	state->m_rfmirror = (ul_rf_mirror == 0);  in init_state()
759 	state->m_if_agc_pol = false;  in init_state()
763 static int drxx_open(struct drxk_state *state)  in drxx_open()  argument
772 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
777 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
780 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
783 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
786 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
789 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
796 static int get_device_capabilities(struct drxk_state *state)  in get_device_capabilities()  argument
807 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
811 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
814 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
817 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
827 		state->m_osc_clock_freq = 27000;  in get_device_capabilities()
831 		state->m_osc_clock_freq = 20250;  in get_device_capabilities()
835 		state->m_osc_clock_freq = 20250;  in get_device_capabilities()
845 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
854 		state->m_device_spin = DRXK_SPIN_A1;  in get_device_capabilities()
858 		state->m_device_spin = DRXK_SPIN_A2;  in get_device_capabilities()
862 		state->m_device_spin = DRXK_SPIN_A3;  in get_device_capabilities()
866 		state->m_device_spin = DRXK_SPIN_UNKNOWN;  in get_device_capabilities()
874 		state->m_has_lna = false;  in get_device_capabilities()
875 		state->m_has_oob = false;  in get_device_capabilities()
876 		state->m_has_atv = false;  in get_device_capabilities()
877 		state->m_has_audio = false;  in get_device_capabilities()
878 		state->m_has_dvbt = true;  in get_device_capabilities()
879 		state->m_has_dvbc = true;  in get_device_capabilities()
880 		state->m_has_sawsw = true;  in get_device_capabilities()
881 		state->m_has_gpio2 = false;  in get_device_capabilities()
882 		state->m_has_gpio1 = false;  in get_device_capabilities()
883 		state->m_has_irqn = false;  in get_device_capabilities()
887 		state->m_has_lna = false;  in get_device_capabilities()
888 		state->m_has_oob = false;  in get_device_capabilities()
889 		state->m_has_atv = true;  in get_device_capabilities()
890 		state->m_has_audio = false;  in get_device_capabilities()
891 		state->m_has_dvbt = true;  in get_device_capabilities()
892 		state->m_has_dvbc = false;  in get_device_capabilities()
893 		state->m_has_sawsw = true;  in get_device_capabilities()
894 		state->m_has_gpio2 = true;  in get_device_capabilities()
895 		state->m_has_gpio1 = true;  in get_device_capabilities()
896 		state->m_has_irqn = false;  in get_device_capabilities()
900 		state->m_has_lna = false;  in get_device_capabilities()
901 		state->m_has_oob = false;  in get_device_capabilities()
902 		state->m_has_atv = true;  in get_device_capabilities()
903 		state->m_has_audio = false;  in get_device_capabilities()
904 		state->m_has_dvbt = true;  in get_device_capabilities()
905 		state->m_has_dvbc = false;  in get_device_capabilities()
906 		state->m_has_sawsw = true;  in get_device_capabilities()
907 		state->m_has_gpio2 = true;  in get_device_capabilities()
908 		state->m_has_gpio1 = true;  in get_device_capabilities()
909 		state->m_has_irqn = false;  in get_device_capabilities()
913 		state->m_has_lna = false;  in get_device_capabilities()
914 		state->m_has_oob = false;  in get_device_capabilities()
915 		state->m_has_atv = true;  in get_device_capabilities()
916 		state->m_has_audio = true;  in get_device_capabilities()
917 		state->m_has_dvbt = true;  in get_device_capabilities()
918 		state->m_has_dvbc = false;  in get_device_capabilities()
919 		state->m_has_sawsw = true;  in get_device_capabilities()
920 		state->m_has_gpio2 = true;  in get_device_capabilities()
921 		state->m_has_gpio1 = true;  in get_device_capabilities()
922 		state->m_has_irqn = false;  in get_device_capabilities()
926 		state->m_has_lna = false;  in get_device_capabilities()
927 		state->m_has_oob = false;  in get_device_capabilities()
928 		state->m_has_atv = true;  in get_device_capabilities()
929 		state->m_has_audio = true;  in get_device_capabilities()
930 		state->m_has_dvbt = true;  in get_device_capabilities()
931 		state->m_has_dvbc = true;  in get_device_capabilities()
932 		state->m_has_sawsw = true;  in get_device_capabilities()
933 		state->m_has_gpio2 = true;  in get_device_capabilities()
934 		state->m_has_gpio1 = true;  in get_device_capabilities()
935 		state->m_has_irqn = false;  in get_device_capabilities()
939 		state->m_has_lna = false;  in get_device_capabilities()
940 		state->m_has_oob = false;  in get_device_capabilities()
941 		state->m_has_atv = true;  in get_device_capabilities()
942 		state->m_has_audio = true;  in get_device_capabilities()
943 		state->m_has_dvbt = true;  in get_device_capabilities()
944 		state->m_has_dvbc = true;  in get_device_capabilities()
945 		state->m_has_sawsw = true;  in get_device_capabilities()
946 		state->m_has_gpio2 = true;  in get_device_capabilities()
947 		state->m_has_gpio1 = true;  in get_device_capabilities()
948 		state->m_has_irqn = false;  in get_device_capabilities()
952 		state->m_has_lna = false;  in get_device_capabilities()
953 		state->m_has_oob = false;  in get_device_capabilities()
954 		state->m_has_atv = true;  in get_device_capabilities()
955 		state->m_has_audio = true;  in get_device_capabilities()
956 		state->m_has_dvbt = true;  in get_device_capabilities()
957 		state->m_has_dvbc = true;  in get_device_capabilities()
958 		state->m_has_sawsw = true;  in get_device_capabilities()
959 		state->m_has_gpio2 = true;  in get_device_capabilities()
960 		state->m_has_gpio1 = true;  in get_device_capabilities()
961 		state->m_has_irqn = false;  in get_device_capabilities()
965 		state->m_has_lna = false;  in get_device_capabilities()
966 		state->m_has_oob = false;  in get_device_capabilities()
967 		state->m_has_atv = true;  in get_device_capabilities()
968 		state->m_has_audio = false;  in get_device_capabilities()
969 		state->m_has_dvbt = true;  in get_device_capabilities()
970 		state->m_has_dvbc = true;  in get_device_capabilities()
971 		state->m_has_sawsw = true;  in get_device_capabilities()
972 		state->m_has_gpio2 = true;  in get_device_capabilities()
973 		state->m_has_gpio1 = true;  in get_device_capabilities()
974 		state->m_has_irqn = false;  in get_device_capabilities()
985 	       state->m_osc_clock_freq / 1000,  in get_device_capabilities()
986 	       state->m_osc_clock_freq % 1000);  in get_device_capabilities()
996 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)  in hi_command()  argument
1004 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
1012 		    ((state->m_hi_cfg_ctrl) &  in hi_command()
1023 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
1029 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1038 static int hi_cfg_command(struct drxk_state *state)  in hi_cfg_command()  argument
1044 	mutex_lock(&state->mutex);  in hi_cfg_command()
1046 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1047 			 state->m_hi_cfg_timeout);  in hi_cfg_command()
1050 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1051 			 state->m_hi_cfg_ctrl);  in hi_cfg_command()
1054 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1055 			 state->m_hi_cfg_wake_up_key);  in hi_cfg_command()
1058 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1059 			 state->m_hi_cfg_bridge_delay);  in hi_cfg_command()
1062 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1063 			 state->m_hi_cfg_timing_div);  in hi_cfg_command()
1066 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1070 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1074 	state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;  in hi_cfg_command()
1076 	mutex_unlock(&state->mutex);  in hi_cfg_command()
1082 static int init_hi(struct drxk_state *state)  in init_hi()  argument
1086 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);  in init_hi()
1087 	state->m_hi_cfg_timeout = 0x96FF;  in init_hi()
1089 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;  in init_hi()
1091 	return hi_cfg_command(state);  in init_hi()
1094 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)  in mpegts_configure_pins()  argument
1103 		state->m_enable_parallel ? "parallel" : "serial");  in mpegts_configure_pins()
1106 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1112 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1118 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1121 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1124 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1127 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1130 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1133 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1136 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1139 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1142 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1145 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1148 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1151 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1157 			((state->m_ts_data_strength <<  in mpegts_configure_pins()
1159 		sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<  in mpegts_configure_pins()
1163 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1167 		if (state->enable_merr_cfg)  in mpegts_configure_pins()
1170 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1173 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1177 		if (state->m_enable_parallel) {  in mpegts_configure_pins()
1179 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1183 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1187 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1191 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1195 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1199 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1203 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1208 			sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<  in mpegts_configure_pins()
1212 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1215 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1218 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1221 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1224 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1227 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1230 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1234 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1237 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1242 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1246 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1253 static int mpegts_disable(struct drxk_state *state)  in mpegts_disable()  argument
1257 	return mpegts_configure_pins(state, false);  in mpegts_disable()
1260 static int bl_chain_cmd(struct drxk_state *state,  in bl_chain_cmd()  argument
1268 	mutex_lock(&state->mutex);  in bl_chain_cmd()
1269 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1272 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1275 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1278 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1285 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1300 	mutex_unlock(&state->mutex);  in bl_chain_cmd()
1305 static int download_microcode(struct drxk_state *state,  in download_microcode()  argument
1358 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1369 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)  in dvbt_enable_ofdm_token_ring()  argument
1384 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1390 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1394 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1407 static int mpegts_stop(struct drxk_state *state)  in mpegts_stop()  argument
1416 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1420 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1425 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1429 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1438 static int scu_command(struct drxk_state *state,  in scu_command()  argument
1461 	mutex_lock(&state->mutex);  in scu_command()
1474 	write_block(state, SCU_RAM_PARAM_0__A -  in scu_command()
1480 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1495 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1534 	mutex_unlock(&state->mutex);  in scu_command()
1538 static int set_iqm_af(struct drxk_state *state, bool active)  in set_iqm_af()  argument
1546 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1564 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1572 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)  in ctrl_power_mode()  argument
1605 	if (state->m_current_power_mode == *mode)  in ctrl_power_mode()
1609 	if (state->m_current_power_mode != DRX_POWER_UP) {  in ctrl_power_mode()
1610 		status = power_up_device(state);  in ctrl_power_mode()
1613 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1630 		switch (state->m_operation_mode) {  in ctrl_power_mode()
1632 			status = mpegts_stop(state);  in ctrl_power_mode()
1635 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1641 			status = mpegts_stop(state);  in ctrl_power_mode()
1644 			status = power_down_qam(state);  in ctrl_power_mode()
1651 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1654 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1657 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1662 			state->m_hi_cfg_ctrl |=  in ctrl_power_mode()
1664 			status = hi_cfg_command(state);  in ctrl_power_mode()
1669 	state->m_current_power_mode = *mode;  in ctrl_power_mode()
1678 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)  in power_down_dvbt()  argument
1687 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1692 		status = scu_command(state,  in power_down_dvbt()
1699 		status = scu_command(state,  in power_down_dvbt()
1708 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1711 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1714 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1719 	status = set_iqm_af(state, false);  in power_down_dvbt()
1725 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1735 static int setoperation_mode(struct drxk_state *state,  in setoperation_mode()  argument
1748 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1754 	if (state->m_operation_mode == o_mode)  in setoperation_mode()
1757 	switch (state->m_operation_mode) {  in setoperation_mode()
1762 		status = mpegts_stop(state);  in setoperation_mode()
1765 		status = power_down_dvbt(state, true);  in setoperation_mode()
1768 		state->m_operation_mode = OM_NONE;  in setoperation_mode()
1772 		status = mpegts_stop(state);  in setoperation_mode()
1775 		status = power_down_qam(state);  in setoperation_mode()
1778 		state->m_operation_mode = OM_NONE;  in setoperation_mode()
1792 		state->m_operation_mode = o_mode;  in setoperation_mode()
1793 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1800 			(state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');  in setoperation_mode()
1801 		state->m_operation_mode = o_mode;  in setoperation_mode()
1802 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1816 static int start(struct drxk_state *state, s32 offset_freq,  in start()  argument
1825 	if (state->m_drxk_state != DRXK_STOPPED &&  in start()
1826 		state->m_drxk_state != DRXK_DTV_STARTED)  in start()
1829 	state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);  in start()
1832 		state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;  in start()
1836 	switch (state->m_operation_mode) {  in start()
1840 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1843 		state->m_drxk_state = DRXK_DTV_STARTED;  in start()
1847 		status = mpegts_stop(state);  in start()
1850 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1853 		status = dvbt_start(state);  in start()
1856 		state->m_drxk_state = DRXK_DTV_STARTED;  in start()
1867 static int shut_down(struct drxk_state *state)  in shut_down()  argument
1871 	mpegts_stop(state);  in shut_down()
1875 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_lock_status()  argument
1887 	switch (state->m_operation_mode) {  in get_lock_status()
1891 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1894 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1898 			state->m_operation_mode, __func__);  in get_lock_status()
1907 static int mpegts_start(struct drxk_state *state)  in mpegts_start()  argument
1914 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1918 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1921 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1928 static int mpegts_dto_init(struct drxk_state *state)  in mpegts_dto_init()  argument
1935 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1938 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1941 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1944 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1947 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1950 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1953 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1956 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1961 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1964 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1967 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1975 static int mpegts_dto_setup(struct drxk_state *state,  in mpegts_dto_setup()  argument
1995 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
1998 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2003 	if (state->m_insert_rs_byte) {  in mpegts_dto_setup()
2014 	if (!state->m_enable_parallel) {  in mpegts_dto_setup()
2021 		max_bit_rate = state->m_dvbt_bitrate;  in mpegts_dto_setup()
2024 		static_clk = state->m_dvbt_static_clk;  in mpegts_dto_setup()
2030 		max_bit_rate = state->m_dvbc_bitrate;  in mpegts_dto_setup()
2031 		static_clk = state->m_dvbc_static_clk;  in mpegts_dto_setup()
2063 		fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)  in mpegts_dto_setup()
2078 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2081 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2084 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2087 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2090 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2093 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2098 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2101 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2105 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2112 static int mpegts_configure_polarity(struct drxk_state *state)  in mpegts_configure_polarity()  argument
2127 	if (state->m_invert_data)  in mpegts_configure_polarity()
2130 	if (state->m_invert_err)  in mpegts_configure_polarity()
2133 	if (state->m_invert_str)  in mpegts_configure_polarity()
2136 	if (state->m_invert_val)  in mpegts_configure_polarity()
2139 	if (state->m_invert_clk)  in mpegts_configure_polarity()
2142 	return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);  in mpegts_configure_polarity()
2147 static int set_agc_rf(struct drxk_state *state,  in set_agc_rf()  argument
2162 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2166 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2169 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2177 		if (state->m_rf_agc_pol)  in set_agc_rf()
2181 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2186 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2195 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2199 		if (is_dvbt(state))  in set_agc_rf()
2200 			p_if_agc_settings = &state->m_dvbt_if_agc_cfg;  in set_agc_rf()
2201 		else if (is_qam(state))  in set_agc_rf()
2202 			p_if_agc_settings = &state->m_qam_if_agc_cfg;  in set_agc_rf()
2204 			p_if_agc_settings = &state->m_atv_if_agc_cfg;  in set_agc_rf()
2212 			status = write16(state,  in set_agc_rf()
2220 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2226 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2235 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2239 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2244 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2248 		if (state->m_rf_agc_pol)  in set_agc_rf()
2252 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2257 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2262 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2270 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2274 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2279 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2283 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2300 static int set_agc_if(struct drxk_state *state,  in set_agc_if()  argument
2313 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2317 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2321 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2329 		if (state->m_if_agc_pol)  in set_agc_if()
2333 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2338 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2346 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2350 		if (is_qam(state))  in set_agc_if()
2351 			p_rf_agc_settings = &state->m_qam_rf_agc_cfg;  in set_agc_if()
2353 			p_rf_agc_settings = &state->m_atv_rf_agc_cfg;  in set_agc_if()
2357 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2366 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2370 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2374 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2382 		if (state->m_if_agc_pol)  in set_agc_if()
2386 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2391 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2400 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2404 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2409 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2413 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2421 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2428 static int get_qam_signal_to_noise(struct drxk_state *state,  in get_qam_signal_to_noise()  argument
2443 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2449 	switch (state->props.modulation) {  in get_qam_signal_to_noise()
2477 static int get_dvbt_signal_to_noise(struct drxk_state *state,  in get_dvbt_signal_to_noise()  argument
2497 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2501 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2505 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2509 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2519 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2528 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2581 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)  in get_signal_to_noise()  argument
2586 	switch (state->m_operation_mode) {  in get_signal_to_noise()
2588 		return get_dvbt_signal_to_noise(state, p_signal_to_noise);  in get_signal_to_noise()
2591 		return get_qam_signal_to_noise(state, p_signal_to_noise);  in get_signal_to_noise()
2599 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2633 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2636 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2642 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2666 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2678 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2682 		switch (state->props.modulation) {
2713 static int get_quality(struct drxk_state *state, s32 *p_quality)
2717 	switch (state->m_operation_mode) {
2719 		return get_dvbt_quality(state, p_quality);
2721 		return get_dvbc_quality(state, p_quality);
2743 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)  in ConfigureI2CBridge()  argument
2749 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in ConfigureI2CBridge()
2751 	if (state->m_drxk_state == DRXK_POWERED_DOWN)  in ConfigureI2CBridge()
2754 	if (state->no_i2c_bridge)  in ConfigureI2CBridge()
2757 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2762 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2767 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2773 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2781 static int set_pre_saw(struct drxk_state *state,  in set_pre_saw()  argument
2792 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2799 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,  in bl_direct_cmd()  argument
2810 	mutex_lock(&state->mutex);  in bl_direct_cmd()
2811 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2814 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2817 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2820 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2823 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2826 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2832 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2845 	mutex_unlock(&state->mutex);  in bl_direct_cmd()
2850 static int adc_sync_measurement(struct drxk_state *state, u16 *count)  in adc_sync_measurement()  argument
2858 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2861 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2866 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2871 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2876 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2888 static int adc_synchronization(struct drxk_state *state)  in adc_synchronization()  argument
2895 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2903 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2916 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2919 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2932 static int set_frequency_shifter(struct drxk_state *state,  in set_frequency_shifter()  argument
2939 	bool tuner_mirror = !state->m_b_mirror_freq_spect;  in set_frequency_shifter()
2944 	u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);  in set_frequency_shifter()
2955 		if ((state->m_operation_mode == OM_QAM_ITU_A) ||  in set_frequency_shifter()
2956 		    (state->m_operation_mode == OM_QAM_ITU_C) ||  in set_frequency_shifter()
2957 		    (state->m_operation_mode == OM_DVBT))  in set_frequency_shifter()
2981 	image_to_select = state->m_rfmirror ^ tuner_mirror ^  in set_frequency_shifter()
2983 	state->m_iqm_fs_rate_ofs =  in set_frequency_shifter()
2987 		state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;  in set_frequency_shifter()
2991 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
2992 			 state->m_iqm_fs_rate_ofs);  in set_frequency_shifter()
2998 static int init_agc(struct drxk_state *state, bool is_dtv)  in init_agc()  argument
3028 	if (!is_qam(state)) {  in init_agc()
3030 		       __func__, state->m_operation_mode);  in init_agc()
3048 	fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;  in init_agc()
3050 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3055 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3058 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3061 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3064 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3067 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3071 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3075 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3078 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3081 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3084 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3087 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3090 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3094 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3098 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3102 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3106 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3109 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3112 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3116 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3119 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3122 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3125 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3128 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3131 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3134 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3137 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3140 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3143 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3146 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3149 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3152 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3155 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3158 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3161 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3164 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3167 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3170 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3175 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3185 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3192 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)  in dvbtqam_get_acc_pkt_err()  argument
3198 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3200 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3207 static int dvbt_sc_command(struct drxk_state *state,  in dvbt_sc_command()  argument
3219 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3231 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3243 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3262 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3266 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3271 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3284 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3291 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3308 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3328 static int power_up_dvbt(struct drxk_state *state)  in power_up_dvbt()  argument
3334 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3340 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)  in dvbt_ctrl_set_inc_enable()  argument
3346 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3348 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3355 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)  in dvbt_ctrl_set_fr_enable()  argument
3363 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3367 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3375 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,  in dvbt_ctrl_set_echo_threshold()  argument
3382 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3403 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3410 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,  in dvbt_ctrl_set_sqi_speed()  argument
3425 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3443 static int dvbt_activate_presets(struct drxk_state *state)  in dvbt_activate_presets()  argument
3453 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3456 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3459 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3462 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3465 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3466 			 state->m_dvbt_if_agc_cfg.ingain_tgt_max);  in dvbt_activate_presets()
3483 static int set_dvbt_standard(struct drxk_state *state,  in set_dvbt_standard()  argument
3492 	power_up_dvbt(state);  in set_dvbt_standard()
3494 	switch_antenna_to_dvbt(state);  in set_dvbt_standard()
3496 	status = scu_command(state,  in set_dvbt_standard()
3504 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3511 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3514 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3517 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3523 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3527 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3531 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3535 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3538 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3542 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3547 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3550 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3553 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3557 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3560 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3563 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3566 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3569 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3574 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3577 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3581 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3586 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3589 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3593 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3596 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3601 	status = adc_synchronization(state);  in set_dvbt_standard()
3604 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3609 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3613 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3616 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3621 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3625 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3630 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3634 	if (!state->m_drxk_a3_rom_code) {  in set_dvbt_standard()
3636 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3637 				 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);  in set_dvbt_standard()
3644 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3647 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3653 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3659 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3663 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3667 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3672 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3676 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3692 static int dvbt_start(struct drxk_state *state)  in dvbt_start()  argument
3702 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3708 	status = mpegts_start(state);  in dvbt_start()
3711 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3729 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,  in set_dvbt()  argument
3743 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3750 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3755 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3758 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3764 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3771 	switch (state->props.transmission_mode) {  in set_dvbt()
3785 	switch (state->props.guard_interval) {  in set_dvbt()
3805 	switch (state->props.hierarchy) {  in set_dvbt()
3826 	switch (state->props.modulation) {  in set_dvbt()
3863 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3869 	switch (state->props.code_rate_HP) {  in set_dvbt()
3904 	switch (state->props.bandwidth_hz) {  in set_dvbt()
3906 		state->props.bandwidth_hz = 8000000;  in set_dvbt()
3910 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3915 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3919 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3923 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3927 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3934 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3939 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3943 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3947 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3951 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3958 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3963 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3967 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3971 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3975 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3999 					((state->m_sys_clock_freq *  in set_dvbt()
4012 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
4023 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
4031 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
4036 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
4039 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
4044 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4056 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4061 	if (!state->m_drxk_a3_rom_code)  in set_dvbt()
4062 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4080 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_dvbt_lock_status()  argument
4096 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4102 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4121 static int power_up_qam(struct drxk_state *state)  in power_up_qam()  argument
4127 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4136 static int power_down_qam(struct drxk_state *state)  in power_down_qam()  argument
4143 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4152 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4155 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4162 	status = set_iqm_af(state, false);  in power_down_qam()
4184 static int set_qam_measurement(struct drxk_state *state,  in set_qam_measurement()  argument
4245 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4248 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4252 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4259 static int set_qam16(struct drxk_state *state)  in set_qam16()  argument
4266 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4269 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4272 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4275 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4278 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4281 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4285 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4288 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4291 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4294 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4297 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4300 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4304 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4307 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4310 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4315 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4321 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4324 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4327 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4330 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4333 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4336 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4339 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4342 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4346 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4349 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4352 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4355 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4358 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4361 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4364 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4367 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4370 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4373 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4376 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4379 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4384 	/* QAM State Machine (FSM) Thresholds */  in set_qam16()
4386 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4389 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4392 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4395 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4398 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4401 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4405 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4408 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4411 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4418 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4421 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4424 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4427 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4430 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4433 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4436 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4453 static int set_qam32(struct drxk_state *state)  in set_qam32()  argument
4461 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4464 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4467 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4470 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4473 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4476 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4481 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4484 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4487 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4490 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4493 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4496 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4500 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4503 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4506 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4512 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4520 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4523 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4526 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4529 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4532 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4535 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4538 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4541 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4545 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4548 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4551 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4554 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4557 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4560 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4563 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4566 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4569 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4572 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4575 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4578 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4583 	/* QAM State Machine (FSM) Thresholds */  in set_qam32()
4585 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4588 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4591 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4594 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4597 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4600 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4604 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4607 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4610 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4617 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4620 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4623 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4626 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4629 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4632 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4635 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4649 static int set_qam64(struct drxk_state *state)  in set_qam64()  argument
4656 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4659 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4662 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4665 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4668 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4671 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4676 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4679 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4682 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4685 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4688 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4691 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4695 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4698 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4701 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4706 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4714 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4717 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4720 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4723 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4726 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4729 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4732 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4735 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4739 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4742 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4745 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4748 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4751 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4754 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4757 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4760 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4763 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4766 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4769 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4772 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4777 	/* QAM State Machine (FSM) Thresholds */  in set_qam64()
4779 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4782 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4785 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4788 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4791 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4794 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4798 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4801 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4804 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4811 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4814 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4817 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4820 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4823 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4826 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4829 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4844 static int set_qam128(struct drxk_state *state)  in set_qam128()  argument
4851 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4854 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4857 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4860 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4863 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4866 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4871 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4874 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4877 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4880 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4883 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4886 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4890 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4893 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4896 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4903 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4911 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4914 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4917 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4920 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4923 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4926 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4929 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4932 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4936 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4939 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4942 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4945 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4948 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4951 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4954 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4957 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4960 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4963 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4966 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4969 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4974 	/* QAM State Machine (FSM) Thresholds */  in set_qam128()
4976 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4979 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4982 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4985 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4988 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
4991 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
4995 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
4998 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
5002 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
5008 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
5011 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
5014 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
5017 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
5020 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
5023 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
5026 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
5041 static int set_qam256(struct drxk_state *state)  in set_qam256()  argument
5048 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5051 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5054 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5057 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5060 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5063 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5068 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5071 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5074 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5077 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5080 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5083 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5087 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5090 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5093 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5099 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5107 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5110 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5113 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5116 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5119 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5122 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5125 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5128 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5132 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5135 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5138 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5141 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5144 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5147 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5150 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5153 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5156 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5159 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5162 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5165 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5170 	/* QAM State Machine (FSM) Thresholds */  in set_qam256()
5172 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5175 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5178 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5181 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5184 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5187 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5191 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5194 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5197 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5204 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5207 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5210 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5213 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5216 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5219 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5222 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5237 static int qam_reset_qam(struct drxk_state *state)  in qam_reset_qam()  argument
5244 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5248 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5265 static int qam_set_symbolrate(struct drxk_state *state)  in qam_set_symbolrate()  argument
5276 	adc_frequency = (state->m_sys_clock_freq * 1000) / 3;  in qam_set_symbolrate()
5278 	if (state->props.symbol_rate <= 1188750)  in qam_set_symbolrate()
5280 	else if (state->props.symbol_rate <= 2377500)  in qam_set_symbolrate()
5282 	else if (state->props.symbol_rate <= 4755000)  in qam_set_symbolrate()
5284 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5291 	symb_freq = state->props.symbol_rate * (1 << ratesel);  in qam_set_symbolrate()
5300 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5303 	state->m_iqm_rc_rate = iqm_rc_rate;  in qam_set_symbolrate()
5307 	symb_freq = state->props.symbol_rate;  in qam_set_symbolrate()
5318 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5335 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_qam_lock_status()  argument
5342 	status = scu_command(state,  in get_qam_lock_status()
5376 static int qam_demodulator_command(struct drxk_state *state,  in qam_demodulator_command()  argument
5383 	set_param_parameters[0] = state->m_constellation;	/* modulation     */  in qam_demodulator_command()
5389 		if (state->m_operation_mode == OM_QAM_ITU_C)  in qam_demodulator_command()
5394 		status = scu_command(state,  in qam_demodulator_command()
5401 		status = scu_command(state,  in qam_demodulator_command()
5407 		if (state->m_operation_mode == OM_QAM_ITU_C)  in qam_demodulator_command()
5417 		status = scu_command(state,  in qam_demodulator_command()
5434 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,  in set_qam()  argument
5439 	int qam_demod_param_count = state->qam_demod_parameter_count;  in set_qam()
5448 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5451 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5454 	status = qam_reset_qam(state);  in set_qam()
5463 	status = qam_set_symbolrate(state);  in set_qam()
5468 	switch (state->props.modulation) {  in set_qam()
5470 		state->m_constellation = DRX_CONSTELLATION_QAM256;  in set_qam()
5474 		state->m_constellation = DRX_CONSTELLATION_QAM64;  in set_qam()
5477 		state->m_constellation = DRX_CONSTELLATION_QAM16;  in set_qam()
5480 		state->m_constellation = DRX_CONSTELLATION_QAM32;  in set_qam()
5483 		state->m_constellation = DRX_CONSTELLATION_QAM128;  in set_qam()
5494 	if (state->qam_demod_parameter_count == 4  in set_qam()
5495 		|| !state->qam_demod_parameter_count) {  in set_qam()
5497 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5503 	if (state->qam_demod_parameter_count == 2  in set_qam()
5504 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5506 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5513 			state->qam_demod_parameter_count,  in set_qam()
5514 			state->microcode_name);  in set_qam()
5516 	} else if (!state->qam_demod_parameter_count) {  in set_qam()
5525 		state->qam_demod_parameter_count = qam_demod_param_count;  in set_qam()
5537 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5543 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5544 				     state->props.symbol_rate);  in set_qam()
5549 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5552 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5557 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5560 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5563 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5566 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5570 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5573 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5576 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5579 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5582 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5585 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5588 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5591 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5594 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5597 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5600 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5603 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5606 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5609 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5612 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5617 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5623 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5628 	switch (state->props.modulation) {  in set_qam()
5630 		status = set_qam16(state);  in set_qam()
5633 		status = set_qam32(state);  in set_qam()
5637 		status = set_qam64(state);  in set_qam()
5640 		status = set_qam128(state);  in set_qam()
5643 		status = set_qam256(state);  in set_qam()
5653 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5660 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5665 	status = mpegts_start(state);  in set_qam()
5668 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5671 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5674 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5679 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5694 static int set_qam_standard(struct drxk_state *state,  in set_qam_standard()  argument
5707 	switch_antenna_to_qam(state);  in set_qam_standard()
5710 	status = power_up_qam(state);  in set_qam_standard()
5714 	status = qam_reset_qam(state);  in set_qam_standard()
5720 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5723 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5731 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5736 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5742 		status = bl_direct_cmd(state,  in set_qam_standard()
5754 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5757 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5760 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5765 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5768 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5771 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5774 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5777 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5781 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5784 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5787 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5790 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5795 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5798 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5801 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5804 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5807 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5810 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5813 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5818 	status = set_iqm_af(state, true);  in set_qam_standard()
5821 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5826 	status = adc_synchronization(state);  in set_qam_standard()
5831 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5836 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5843 	status = init_agc(state, true);  in set_qam_standard()
5846 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5851 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5854 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5859 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5866 static int write_gpio(struct drxk_state *state)  in write_gpio()  argument
5873 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5879 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5883 	if (state->m_has_sawsw) {  in write_gpio()
5884 		if (state->uio_mask & 0x0001) { /* UIO-1 */  in write_gpio()
5886 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5887 					 state->m_gpio_cfg);  in write_gpio()
5892 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5895 			if ((state->m_gpio & 0x0001) == 0)  in write_gpio()
5900 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5904 		if (state->uio_mask & 0x0002) { /* UIO-2 */  in write_gpio()
5906 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5907 					 state->m_gpio_cfg);  in write_gpio()
5912 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5915 			if ((state->m_gpio & 0x0002) == 0)  in write_gpio()
5920 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5924 		if (state->uio_mask & 0x0004) { /* UIO-3 */  in write_gpio()
5926 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5927 					 state->m_gpio_cfg);  in write_gpio()
5932 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5935 			if ((state->m_gpio & 0x0004) == 0)  in write_gpio()
5940 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5946 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5953 static int switch_antenna_to_qam(struct drxk_state *state)  in switch_antenna_to_qam()  argument
5960 	if (!state->antenna_gpio)  in switch_antenna_to_qam()
5963 	gpio_state = state->m_gpio & state->antenna_gpio;  in switch_antenna_to_qam()
5965 	if (state->antenna_dvbt ^ gpio_state) {  in switch_antenna_to_qam()
5967 		if (state->antenna_dvbt)  in switch_antenna_to_qam()
5968 			state->m_gpio &= ~state->antenna_gpio;  in switch_antenna_to_qam()
5970 			state->m_gpio |= state->antenna_gpio;  in switch_antenna_to_qam()
5971 		status = write_gpio(state);  in switch_antenna_to_qam()
5978 static int switch_antenna_to_dvbt(struct drxk_state *state)  in switch_antenna_to_dvbt()  argument
5985 	if (!state->antenna_gpio)  in switch_antenna_to_dvbt()
5988 	gpio_state = state->m_gpio & state->antenna_gpio;  in switch_antenna_to_dvbt()
5990 	if (!(state->antenna_dvbt ^ gpio_state)) {  in switch_antenna_to_dvbt()
5992 		if (state->antenna_dvbt)  in switch_antenna_to_dvbt()
5993 			state->m_gpio |= state->antenna_gpio;  in switch_antenna_to_dvbt()
5995 			state->m_gpio &= ~state->antenna_gpio;  in switch_antenna_to_dvbt()
5996 		status = write_gpio(state);  in switch_antenna_to_dvbt()
6004 static int power_down_device(struct drxk_state *state)  in power_down_device()  argument
6015 	if (state->m_b_p_down_open_bridge) {  in power_down_device()
6017 		status = ConfigureI2CBridge(state, true);  in power_down_device()
6022 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
6026 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
6030 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
6033 	state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;  in power_down_device()
6034 	status = hi_cfg_command(state);  in power_down_device()
6042 static int init_drxk(struct drxk_state *state)  in init_drxk()  argument
6049 	if (state->m_drxk_state == DRXK_UNINITIALIZED) {  in init_drxk()
6050 		drxk_i2c_lock(state);  in init_drxk()
6051 		status = power_up_device(state);  in init_drxk()
6054 		status = drxx_open(state);  in init_drxk()
6058 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6064 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6072 		state->m_drxk_a3_patch_code = true;  in init_drxk()
6073 		status = get_device_capabilities(state);  in init_drxk()
6080 		state->m_hi_cfg_bridge_delay =  in init_drxk()
6081 			(u16) ((state->m_osc_clock_freq / 1000) *  in init_drxk()
6084 		if (state->m_hi_cfg_bridge_delay >  in init_drxk()
6086 			state->m_hi_cfg_bridge_delay =  in init_drxk()
6090 		state->m_hi_cfg_bridge_delay +=  in init_drxk()
6091 			state->m_hi_cfg_bridge_delay <<  in init_drxk()
6094 		status = init_hi(state);  in init_drxk()
6099 		if (!(state->m_DRXK_A1_ROM_CODE)  in init_drxk()
6100 			&& !(state->m_DRXK_A2_ROM_CODE))  in init_drxk()
6103 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6110 		status = mpegts_disable(state);  in init_drxk()
6115 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6118 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6123 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6129 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6133 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6137 		if (state->fw) {  in init_drxk()
6138 			status = download_microcode(state, state->fw->data,  in init_drxk()
6139 						   state->fw->size);  in init_drxk()
6145 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6151 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6154 		status = drxx_open(state);  in init_drxk()
6161 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6176 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6185 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6205 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6211 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6215 		status = mpegts_dto_init(state);  in init_drxk()
6218 		status = mpegts_stop(state);  in init_drxk()
6221 		status = mpegts_configure_polarity(state);  in init_drxk()
6224 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6228 		status = write_gpio(state);  in init_drxk()
6232 		state->m_drxk_state = DRXK_STOPPED;  in init_drxk()
6234 		if (state->m_b_power_down) {  in init_drxk()
6235 			status = power_down_device(state);  in init_drxk()
6238 			state->m_drxk_state = DRXK_POWERED_DOWN;  in init_drxk()
6240 			state->m_drxk_state = DRXK_STOPPED;  in init_drxk()
6244 		if (state->m_has_dvbc) {  in init_drxk()
6245 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;  in init_drxk()
6246 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;  in init_drxk()
6247 			strlcat(state->frontend.ops.info.name, " DVB-C",  in init_drxk()
6248 				sizeof(state->frontend.ops.info.name));  in init_drxk()
6250 		if (state->m_has_dvbt) {  in init_drxk()
6251 			state->frontend.ops.delsys[n++] = SYS_DVBT;  in init_drxk()
6252 			strlcat(state->frontend.ops.info.name, " DVB-T",  in init_drxk()
6253 				sizeof(state->frontend.ops.info.name));  in init_drxk()
6255 		drxk_i2c_unlock(state);  in init_drxk()
6259 		state->m_drxk_state = DRXK_NO_DEV;  in init_drxk()
6260 		drxk_i2c_unlock(state);  in init_drxk()
6270 	struct drxk_state *state = context;  in load_firmware_cb()  local
6275 			state->microcode_name);  in load_firmware_cb()
6277 			state->microcode_name);  in load_firmware_cb()
6278 		state->microcode_name = NULL;  in load_firmware_cb()
6291 	state->fw = fw;  in load_firmware_cb()
6293 	init_drxk(state);  in load_firmware_cb()
6298 	struct drxk_state *state = fe->demodulator_priv;  in drxk_release()  local
6301 	release_firmware(state->fw);  in drxk_release()
6303 	kfree(state);  in drxk_release()
6308 	struct drxk_state *state = fe->demodulator_priv;  in drxk_sleep()  local
6312 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_sleep()
6314 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_sleep()
6317 	shut_down(state);  in drxk_sleep()
6323 	struct drxk_state *state = fe->demodulator_priv;  in drxk_gate_ctrl()  local
6327 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_gate_ctrl()
6330 	return ConfigureI2CBridge(state, enable ? true : false);  in drxk_gate_ctrl()
6337 	struct drxk_state *state = fe->demodulator_priv;  in drxk_set_parameters()  local
6342 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_set_parameters()
6345 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_set_parameters()
6360 	old_delsys = state->props.delivery_system;  in drxk_set_parameters()
6361 	state->props = *p;  in drxk_set_parameters()
6364 		shut_down(state);  in drxk_set_parameters()
6368 			if (!state->m_has_dvbc)  in drxk_set_parameters()
6370 			state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?  in drxk_set_parameters()
6372 			if (state->m_itut_annex_c)  in drxk_set_parameters()
6373 				setoperation_mode(state, OM_QAM_ITU_C);  in drxk_set_parameters()
6375 				setoperation_mode(state, OM_QAM_ITU_A);  in drxk_set_parameters()
6378 			if (!state->m_has_dvbt)  in drxk_set_parameters()
6380 			setoperation_mode(state, OM_DVBT);  in drxk_set_parameters()
6388 	start(state, 0, IF);  in drxk_set_parameters()
6405 static int get_strength(struct drxk_state *state, u64 *strength)  in get_strength()  argument
6420 	if (is_dvbt(state)) {  in get_strength()
6421 		rf_agc = state->m_dvbt_rf_agc_cfg;  in get_strength()
6422 		if_agc = state->m_dvbt_if_agc_cfg;  in get_strength()
6423 	} else if (is_qam(state)) {  in get_strength()
6424 		rf_agc = state->m_qam_rf_agc_cfg;  in get_strength()
6425 		if_agc = state->m_qam_if_agc_cfg;  in get_strength()
6427 		rf_agc = state->m_atv_rf_agc_cfg;  in get_strength()
6428 		if_agc = state->m_atv_if_agc_cfg;  in get_strength()
6433 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6438 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6466 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6471 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6509 	struct drxk_state *state = fe->demodulator_priv;  in drxk_get_stats()  local
6522 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_get_stats()
6524 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_get_stats()
6528 	state->fe_status = 0;  in drxk_get_stats()
6529 	get_lock_status(state, &stat);  in drxk_get_stats()
6531 		state->fe_status |= 0x1f;  in drxk_get_stats()
6533 		state->fe_status |= 0x0f;  in drxk_get_stats()
6535 		state->fe_status |= 0x07;  in drxk_get_stats()
6540 	get_strength(state, &c->strength.stat[0].uvalue);  in drxk_get_stats()
6545 		get_signal_to_noise(state, &cnr);  in drxk_get_stats()
6573 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6578 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6584 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6589 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6594 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6599 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6603 	write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in drxk_get_stats()
6632 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_status()  local
6641 	*status = state->fe_status;  in drxk_read_status()
6649 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_signal_strength()  local
6654 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_signal_strength()
6656 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_signal_strength()
6665 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_snr()  local
6670 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_snr()
6672 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_snr()
6675 	get_signal_to_noise(state, &snr2);  in drxk_read_snr()
6686 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_ucblocks()  local
6691 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_ucblocks()
6693 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_ucblocks()
6696 	dvbtqam_get_acc_pkt_err(state, &err);  in drxk_read_ucblocks()
6704 	struct drxk_state *state = fe->demodulator_priv;  in drxk_get_tune_settings()  local
6709 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_get_tune_settings()
6711 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_get_tune_settings()
6764 	struct drxk_state *state = NULL;  in drxk_attach()  local
6769 	state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);  in drxk_attach()
6770 	if (!state)  in drxk_attach()
6773 	state->i2c = i2c;  in drxk_attach()
6774 	state->demod_address = adr;  in drxk_attach()
6775 	state->single_master = config->single_master;  in drxk_attach()
6776 	state->microcode_name = config->microcode_name;  in drxk_attach()
6777 	state->qam_demod_parameter_count = config->qam_demod_parameter_count;  in drxk_attach()
6778 	state->no_i2c_bridge = config->no_i2c_bridge;  in drxk_attach()
6779 	state->antenna_gpio = config->antenna_gpio;  in drxk_attach()
6780 	state->antenna_dvbt = config->antenna_dvbt;  in drxk_attach()
6781 	state->m_chunk_size = config->chunk_size;  in drxk_attach()
6782 	state->enable_merr_cfg = config->enable_merr_cfg;  in drxk_attach()
6785 		state->m_dvbt_static_clk = false;  in drxk_attach()
6786 		state->m_dvbc_static_clk = false;  in drxk_attach()
6788 		state->m_dvbt_static_clk = true;  in drxk_attach()
6789 		state->m_dvbc_static_clk = true;  in drxk_attach()
6794 		state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;  in drxk_attach()
6796 		state->m_ts_clockk_strength = 0x06;  in drxk_attach()
6799 		state->m_enable_parallel = true;  in drxk_attach()
6801 		state->m_enable_parallel = false;  in drxk_attach()
6804 	state->uio_mask = config->antenna_gpio;  in drxk_attach()
6807 	if (!state->antenna_dvbt && state->antenna_gpio)  in drxk_attach()
6808 		state->m_gpio |= state->antenna_gpio;  in drxk_attach()
6810 		state->m_gpio &= ~state->antenna_gpio;  in drxk_attach()
6812 	mutex_init(&state->mutex);  in drxk_attach()
6814 	memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));  in drxk_attach()
6815 	state->frontend.demodulator_priv = state;  in drxk_attach()
6817 	init_state(state);  in drxk_attach()
6820 	if (state->microcode_name) {  in drxk_attach()
6823 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6824 					  state->i2c->dev.parent);  in drxk_attach()
6827 		load_firmware_cb(fw, state);  in drxk_attach()
6828 	} else if (init_drxk(state) < 0)  in drxk_attach()
6833 	p = &state->frontend.dtv_property_cache;  in drxk_attach()
6853 	return &state->frontend;  in drxk_attach()
6857 	kfree(state);  in drxk_attach()