Lines Matching full:single
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
111 * Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch
112 * + single master mode means no use of repeated starts
114 * Default is single master.
118 * Single/multi master selected via the flags in the FASI protocol.
119 * + single master means remember memory address between i2c packets
121 * Default is single master, DAP FASI changes multi-master setting silently
122 * into single master setting. This cannot be overridden.
134 * Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and
139 * In single master mode, data can be written by sending the register address
146 * Data in single master mode is transferred as follows:
170 * | single | multi | single | multi |
201 #error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
209 #error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
244 #define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */