55 	int hw_irq;  member
115 						   int reg, int hw_irq)  in intc_irqpin_hwirq_mask()  argument
117 	return BIT((p->iomem[reg].width - 1) - hw_irq);  in intc_irqpin_hwirq_mask()
121 					       int reg, int hw_irq)  in intc_irqpin_irq_write_hwirq()  argument
123 	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));  in intc_irqpin_irq_write_hwirq()
176 		str, i->requested_irq, i->hw_irq, i->domain_irq);  in intc_irqpin_dbg()
182 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_enable()  local
184 	intc_irqpin_dbg(&p->irq[hw_irq], "enable");  in intc_irqpin_irq_enable()
185 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);  in intc_irqpin_irq_enable()
191 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_disable()  local
193 	intc_irqpin_dbg(&p->irq[hw_irq], "disable");  in intc_irqpin_irq_disable()
194 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);  in intc_irqpin_irq_disable()
200 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_shared_irq_enable()  local
202 	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");  in intc_irqpin_shared_irq_enable()
203 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);  in intc_irqpin_shared_irq_enable()
205 	p->shared_irq_mask &= ~BIT(hw_irq);  in intc_irqpin_shared_irq_enable()
211 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_shared_irq_disable()  local
213 	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");  in intc_irqpin_shared_irq_disable()
214 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);  in intc_irqpin_shared_irq_disable()
216 	p->shared_irq_mask |= BIT(hw_irq);  in intc_irqpin_shared_irq_disable()
272 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_set_wake()  local
274 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);  in intc_irqpin_irq_set_wake()
290 	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);  in intc_irqpin_irq_handler()
335 	p->irq[hw].hw_irq = hw;  in intc_irqpin_irq_domain_map()