35 static void mvebu_pic_reset(struct mvebu_pic *pic)  in mvebu_pic_reset()  argument
38 	writel(0, pic->base + PIC_MASK);  in mvebu_pic_reset()
39 	writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);  in mvebu_pic_reset()
44 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_eoi_irq()  local
46 	writel(1 << d->hwirq, pic->base + PIC_CAUSE);  in mvebu_pic_eoi_irq()
51 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_mask_irq()  local
54 	reg =  readl(pic->base + PIC_MASK);  in mvebu_pic_mask_irq()
56 	writel(reg, pic->base + PIC_MASK);  in mvebu_pic_mask_irq()
61 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_unmask_irq()  local
64 	reg = readl(pic->base + PIC_MASK);  in mvebu_pic_unmask_irq()
66 	writel(reg, pic->base + PIC_MASK);  in mvebu_pic_unmask_irq()
72 	struct mvebu_pic *pic = domain->host_data;  in mvebu_pic_irq_map()  local
75 	irq_set_chip_data(virq, pic);  in mvebu_pic_irq_map()
76 	irq_set_chip_and_handler(virq, &pic->irq_chip,  in mvebu_pic_irq_map()
91 	struct mvebu_pic *pic = irq_desc_get_handler_data(desc);  in mvebu_pic_handle_cascade_irq()  local
96 	irqmap = readl_relaxed(pic->base + PIC_CAUSE);  in mvebu_pic_handle_cascade_irq()
100 		cascade_irq = irq_find_mapping(pic->domain, irqn);  in mvebu_pic_handle_cascade_irq()
109 	struct mvebu_pic *pic = data;  in mvebu_pic_enable_percpu_irq()  local
111 	mvebu_pic_reset(pic);  in mvebu_pic_enable_percpu_irq()
112 	enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);  in mvebu_pic_enable_percpu_irq()
117 	struct mvebu_pic *pic = data;  in mvebu_pic_disable_percpu_irq()  local
119 	disable_percpu_irq(pic->parent_irq);  in mvebu_pic_disable_percpu_irq()
125 	struct mvebu_pic *pic;  in mvebu_pic_probe()  local
129 	pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);  in mvebu_pic_probe()
130 	if (!pic)  in mvebu_pic_probe()
134 	pic->base = devm_ioremap_resource(&pdev->dev, res);  in mvebu_pic_probe()
135 	if (IS_ERR(pic->base))  in mvebu_pic_probe()
136 		return PTR_ERR(pic->base);  in mvebu_pic_probe()
138 	irq_chip = &pic->irq_chip;  in mvebu_pic_probe()
144 	pic->parent_irq = irq_of_parse_and_map(node, 0);  in mvebu_pic_probe()
145 	if (pic->parent_irq <= 0) {  in mvebu_pic_probe()
150 	pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS,  in mvebu_pic_probe()
151 					    &mvebu_pic_domain_ops, pic);  in mvebu_pic_probe()
152 	if (!pic->domain) {  in mvebu_pic_probe()
157 	irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);  in mvebu_pic_probe()
158 	irq_set_handler_data(pic->parent_irq, pic);  in mvebu_pic_probe()
160 	on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);  in mvebu_pic_probe()
162 	platform_set_drvdata(pdev, pic);  in mvebu_pic_probe()
169 	struct mvebu_pic *pic = platform_get_drvdata(pdev);  in mvebu_pic_remove()  local
171 	on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);  in mvebu_pic_remove()
172 	irq_domain_remove(pic->domain);  in mvebu_pic_remove()