75 	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);  in ixp4xx_irq_mask()  local
78 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_mask()
79 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
81 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
83 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
85 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
95 	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);  in ixp4xx_irq_unmask()  local
98 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_unmask()
99 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
101 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
103 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
105 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
111 	struct ixp4xx_irq *ixi = &ixirq;  in ixp4xx_handle_irq()  local
115 	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);  in ixp4xx_handle_irq()
117 		handle_domain_irq(ixi->domain, i, regs);  in ixp4xx_handle_irq()
122 	if (ixi->is_356) {  in ixp4xx_handle_irq()
123 		status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);  in ixp4xx_handle_irq()
125 			handle_domain_irq(ixi->domain, i + 32, regs);  in ixp4xx_handle_irq()
157 	struct ixp4xx_irq *ixi = d->host_data;  in ixp4xx_irq_domain_alloc()  local
178 				    &ixi->irqchip,  in ixp4xx_irq_domain_alloc()
179 				    ixi,  in ixp4xx_irq_domain_alloc()
205 	struct ixp4xx_irq *ixi = &ixirq;  in ixp4xx_get_irq_domain()  local
207 	return ixi->domain;  in ixp4xx_get_irq_domain()
255 static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,  in ixp4xx_irq_setup()  argument
262 	ixi->irqbase = irqbase;  in ixp4xx_irq_setup()
263 	ixi->is_356 = is_356;  in ixp4xx_irq_setup()
266 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);  in ixp4xx_irq_setup()
269 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_setup()
273 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);  in ixp4xx_irq_setup()
276 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_setup()
283 	ixi->irqchip.name = "IXP4xx";  in ixp4xx_irq_setup()
284 	ixi->irqchip.irq_mask = ixp4xx_irq_mask;  in ixp4xx_irq_setup()
285 	ixi->irqchip.irq_unmask	= ixp4xx_irq_unmask;  in ixp4xx_irq_setup()
286 	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;  in ixp4xx_irq_setup()
288 	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,  in ixp4xx_irq_setup()
290 					       ixi);  in ixp4xx_irq_setup()
291 	if (!ixi->domain) {  in ixp4xx_irq_setup()
309 	struct ixp4xx_irq *ixi = &ixirq;  in ixp4xx_irq_init()  local
327 	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);  in ixp4xx_irq_init()
351 		ret = __irq_domain_alloc_irqs(ixi->domain,  in ixp4xx_irq_init()
371 	struct ixp4xx_irq *ixi = &ixirq;  in ixp4xx_of_init_irq()  local
389 	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);  in ixp4xx_of_init_irq()