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315 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
324 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
333 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
347 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
356 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
390 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
402 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
426 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
438 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
443 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
532 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
540 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
549 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
570 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
582 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
597 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
603 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
614 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
627 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
632 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
652 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
658 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
664 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
673 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
685 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
694 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
708 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
716 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
722 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
728 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
737 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
754 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
764 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
770 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
776 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
782 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
788 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
794 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
806 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
818 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
824 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
830 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
840 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
849 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
861 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
875 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
883 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
889 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
922 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
931 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
958 #define V2_CQE_BYTE_32_LPK_S 31
989 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
1008 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1023 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1037 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1099 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1105 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1117 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1130 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1142 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1154 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1198 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1294 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1582 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1626 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1677 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1678 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1728 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1738 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1745 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1749 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1753 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1767 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1771 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1778 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1782 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)