102 	writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);  in efa_com_reg_read32()
155 	sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);  in efa_com_admin_init_sq()
160 	writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);  in efa_com_admin_init_sq()
161 	writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);  in efa_com_admin_init_sq()
168 	writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);  in efa_com_admin_init_sq()
195 	writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);  in efa_com_admin_init_cq()
196 	writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);  in efa_com_admin_init_cq()
206 	writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);  in efa_com_admin_init_cq()
237 	writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);  in efa_com_admin_init_aenq()
238 	writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);  in efa_com_admin_init_aenq()
247 	writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);  in efa_com_admin_init_aenq()
253 	writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);  in efa_com_admin_init_aenq()
707 	writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);  in efa_com_set_admin_polling_mode()
893 	writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);  in efa_com_aenq_intr_handler()
906 	writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);  in efa_com_mmio_reg_read_resp_addr_init()
907 	writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);  in efa_com_mmio_reg_read_resp_addr_init()
1069 	writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);  in efa_com_dev_reset()
1082 	writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);  in efa_com_dev_reset()