Lines Matching refs:st
67 static int adf4350_sync_config(struct adf4350_state *st) in adf4350_sync_config() argument
72 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
81 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
82 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
85 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
86 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
87 i, (u32)st->regs[i] | i); in adf4350_sync_config()
97 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_reg_access() local
105 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); in adf4350_reg_access()
106 ret = adf4350_sync_config(st); in adf4350_reg_access()
108 *readval = st->regs_hw[reg]; in adf4350_reg_access()
116 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) in adf4350_tune_r_cnt() argument
118 struct adf4350_platform_data *pdata = st->pdata; in adf4350_tune_r_cnt()
122 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / in adf4350_tune_r_cnt()
124 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); in adf4350_tune_r_cnt()
129 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) in adf4350_set_freq() argument
131 struct adf4350_platform_data *pdata = st->pdata; in adf4350_set_freq()
137 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) in adf4350_set_freq()
148 st->r4_rf_div_sel = 0; in adf4350_set_freq()
152 st->r4_rf_div_sel++; in adf4350_set_freq()
162 chspc = st->chspc; in adf4350_set_freq()
167 r_cnt = adf4350_tune_r_cnt(st, r_cnt); in adf4350_set_freq()
168 st->r1_mod = st->fpfd / chspc; in adf4350_set_freq()
174 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); in adf4350_set_freq()
177 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); in adf4350_set_freq()
178 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ in adf4350_set_freq()
179 st->r0_fract = do_div(tmp, st->r1_mod); in adf4350_set_freq()
180 st->r0_int = tmp; in adf4350_set_freq()
181 } while (mdiv > st->r0_int); in adf4350_set_freq()
183 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); in adf4350_set_freq()
185 if (st->r0_fract && st->r1_mod) { in adf4350_set_freq()
186 div_gcd = gcd(st->r1_mod, st->r0_fract); in adf4350_set_freq()
187 st->r1_mod /= div_gcd; in adf4350_set_freq()
188 st->r0_fract /= div_gcd; in adf4350_set_freq()
190 st->r0_fract = 0; in adf4350_set_freq()
191 st->r1_mod = 1; in adf4350_set_freq()
194 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" in adf4350_set_freq()
197 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, in adf4350_set_freq()
198 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", in adf4350_set_freq()
201 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | in adf4350_set_freq()
202 ADF4350_REG0_FRACT(st->r0_fract); in adf4350_set_freq()
204 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | in adf4350_set_freq()
205 ADF4350_REG1_MOD(st->r1_mod) | in adf4350_set_freq()
208 st->regs[ADF4350_REG2] = in adf4350_set_freq()
218 st->regs[ADF4350_REG3] = pdata->r3_user_settings & in adf4350_set_freq()
226 st->regs[ADF4350_REG4] = in adf4350_set_freq()
228 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | in adf4350_set_freq()
238 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; in adf4350_set_freq()
239 st->freq_req = freq; in adf4350_set_freq()
241 return adf4350_sync_config(st); in adf4350_set_freq()
249 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_write() local
261 ret = adf4350_set_freq(st, readin); in adf4350_write()
269 if (st->clk) { in adf4350_write()
270 tmp = clk_round_rate(st->clk, readin); in adf4350_write()
275 ret = clk_set_rate(st->clk, tmp); in adf4350_write()
279 st->clkin = readin; in adf4350_write()
280 ret = adf4350_set_freq(st, st->freq_req); in adf4350_write()
286 st->chspc = readin; in adf4350_write()
290 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
292 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
294 adf4350_sync_config(st); in adf4350_write()
309 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_read() local
316 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * in adf4350_read()
317 (u64)st->fpfd; in adf4350_read()
318 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); in adf4350_read()
320 if (gpio_is_valid(st->pdata->gpio_lock_detect)) in adf4350_read()
321 if (!gpio_get_value(st->pdata->gpio_lock_detect)) { in adf4350_read()
322 dev_dbg(&st->spi->dev, "PLL un-locked\n"); in adf4350_read()
327 if (st->clk) in adf4350_read()
328 st->clkin = clk_get_rate(st->clk); in adf4350_read()
330 val = st->clkin; in adf4350_read()
333 val = st->chspc; in adf4350_read()
336 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); in adf4350_read()
496 struct adf4350_state *st; in adf4350_probe() local
523 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in adf4350_probe()
529 st = iio_priv(indio_dev); in adf4350_probe()
531 st->reg = devm_regulator_get(&spi->dev, "vcc"); in adf4350_probe()
532 if (!IS_ERR(st->reg)) { in adf4350_probe()
533 ret = regulator_enable(st->reg); in adf4350_probe()
539 st->spi = spi; in adf4350_probe()
540 st->pdata = pdata; in adf4350_probe()
551 st->chspc = pdata->channel_spacing; in adf4350_probe()
553 st->clk = clk; in adf4350_probe()
554 st->clkin = clk_get_rate(clk); in adf4350_probe()
556 st->clkin = pdata->clkin; in adf4350_probe()
559 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? in adf4350_probe()
562 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); in adf4350_probe()
576 ret = adf4350_set_freq(st, pdata->power_up_frequency); in adf4350_probe()
588 if (!IS_ERR(st->reg)) in adf4350_probe()
589 regulator_disable(st->reg); in adf4350_probe()
600 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_remove() local
601 struct regulator *reg = st->reg; in adf4350_remove()
603 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_remove()
604 adf4350_sync_config(st); in adf4350_remove()
608 if (st->clk) in adf4350_remove()
609 clk_disable_unprepare(st->clk); in adf4350_remove()