331 #define at91_adc_writel(st, reg, val)	writel_relaxed(val, st->base + reg)  macro
516 	at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);  in at91_adc_config_emr()
569 		at91_adc_writel(st, AT91_SAMA5D2_IDR,  in at91_adc_configure_touch()
571 		at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);  in at91_adc_configure_touch()
597 	at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);  in at91_adc_configure_touch()
602 	at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);  in at91_adc_configure_touch()
609 	at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);  in at91_adc_configure_touch()
722 	at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);  in at91_adc_configure_trigger()
735 			at91_adc_writel(st, AT91_SAMA5D2_CHER,  in at91_adc_configure_trigger()
739 				at91_adc_writel(st, AT91_SAMA5D2_IER,  in at91_adc_configure_trigger()
745 				at91_adc_writel(st, AT91_SAMA5D2_IDR,  in at91_adc_configure_trigger()
748 			at91_adc_writel(st, AT91_SAMA5D2_CHDR,  in at91_adc_configure_trigger()
864 	at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);  in at91_adc_dma_start()
1157 	at91_adc_writel(st, AT91_SAMA5D2_MR, mr);  in at91_adc_setup_samp_freq()
1203 	at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);  in at91_adc_pen_detect_interrupt()
1204 	at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |  in at91_adc_pen_detect_interrupt()
1207 	at91_adc_writel(st, AT91_SAMA5D2_TRGR,  in at91_adc_pen_detect_interrupt()
1217 	at91_adc_writel(st, AT91_SAMA5D2_TRGR,  in at91_adc_no_pen_detect_interrupt()
1219 	at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |  in at91_adc_no_pen_detect_interrupt()
1226 	at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);  in at91_adc_no_pen_detect_interrupt()
1340 	at91_adc_writel(st, AT91_SAMA5D2_COR, cor);  in at91_adc_read_info_raw()
1341 	at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));  in at91_adc_read_info_raw()
1342 	at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));  in at91_adc_read_info_raw()
1343 	at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);  in at91_adc_read_info_raw()
1359 	at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));  in at91_adc_read_info_raw()
1360 	at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));  in at91_adc_read_info_raw()
1563 	at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);  in at91_adc_hw_init()
1564 	at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);  in at91_adc_hw_init()
1569 	at91_adc_writel(st, AT91_SAMA5D2_MR,  in at91_adc_hw_init()
1851 	at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);  in at91_adc_suspend()