1 // SPDX-License-Identifier: GPL-2.0-only
3  * i2c-xiic.c
4  * Copyright (c) 2002-2007 Xilinx Inc.
5  * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48  * struct xiic_i2c - Internal representation of the XIIC I2C bus
57  * @rx_msg:	Current RX message
58  * @rx_pos:	Position within current RX message
59  * @endianness: big/little-endian byte order
88 #define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)	/* Data Rx Register   */
90 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)	/* Tx FIFO Occupancy  */
91 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)	/* Rx FIFO Occupancy  */
93 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)	/* Rx FIFO Depth reg  */
98 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02	/* Transmit FIFO reset=1  */
109 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08	/* 1=Dir: mstr <-- slave  */
110 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10	/* 1 = Tx FIFO full       */
111 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20	/* 1 = Rx FIFO full       */
112 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40	/* 1 = Rx FIFO empty      */
113 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80	/* 1 = Tx FIFO empty      */
118 #define XIIC_INTR_TX_EMPTY_MASK           0x04	/* 1 = Tx FIFO/reg empty  */
119 #define XIIC_INTR_RX_FULL_MASK            0x08	/* 1=Rx FIFO/reg=OCY level */
123 #define XIIC_INTR_TX_HALF_MASK            0x80	/* 1 = TX FIFO half empty */
125 /* The following constants specify the depth of the FIFOs */
126 #define IIC_RX_FIFO_DEPTH         16	/* Rx fifo capacity               */
127 #define IIC_TX_FIFO_DEPTH         16	/* Tx fifo capacity               */
138  * Tx Fifo upper bit masks.
164 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
165 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
171  * For the register read and write functions, a little-endian and big-endian
175  * big-endian systems.
180 	if (i2c->endianness == LITTLE)  in xiic_setreg8()
181 		iowrite8(value, i2c->base + reg);  in xiic_setreg8()
183 		iowrite8(value, i2c->base + reg + 3);  in xiic_setreg8()
190 	if (i2c->endianness == LITTLE)  in xiic_getreg8()
191 		ret = ioread8(i2c->base + reg);  in xiic_getreg8()
193 		ret = ioread8(i2c->base + reg + 3);  in xiic_getreg8()
199 	if (i2c->endianness == LITTLE)  in xiic_setreg16()
200 		iowrite16(value, i2c->base + reg);  in xiic_setreg16()
202 		iowrite16be(value, i2c->base + reg + 2);  in xiic_setreg16()
207 	if (i2c->endianness == LITTLE)  in xiic_setreg32()
208 		iowrite32(value, i2c->base + reg);  in xiic_setreg32()
210 		iowrite32be(value, i2c->base + reg);  in xiic_setreg32()
217 	if (i2c->endianness == LITTLE)  in xiic_getreg32()
218 		ret = ioread32(i2c->base + reg);  in xiic_getreg32()
220 		ret = ioread32be(i2c->base + reg);  in xiic_getreg32()
261 	/* Set receive Fifo depth to maximum (zero based). */  in xiic_reinit()
262 	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);  in xiic_reinit()
264 	/* Reset Tx Fifo. */  in xiic_reinit()
267 	/* Enable IIC Device, remove Tx Fifo reset & disable general call. */  in xiic_reinit()
270 	/* make sure RX fifo is empty */  in xiic_reinit()
297 	dev_dbg(i2c->adap.dev.parent,  in xiic_read_rx()
298 		"%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",  in xiic_read_rx()
307 		i2c->rx_msg->buf[i2c->rx_pos++] =  in xiic_read_rx()
312 		IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);  in xiic_read_rx()
317 	/* return the actual space left in the FIFO */  in xiic_tx_fifo_space()
318 	return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;  in xiic_tx_fifo_space()
328 	dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",  in xiic_fill_tx_fifo()
331 	while (len--) {  in xiic_fill_tx_fifo()
332 		u16 data = i2c->tx_msg->buf[i2c->tx_pos++];  in xiic_fill_tx_fifo()
333 		if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {  in xiic_fill_tx_fifo()
334 			/* last message in transfer -> STOP */  in xiic_fill_tx_fifo()
336 			dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);  in xiic_fill_tx_fifo()
344 	i2c->tx_msg = NULL;  in xiic_wakeup()
345 	i2c->rx_msg = NULL;  in xiic_wakeup()
346 	i2c->nmsgs = 0;  in xiic_wakeup()
347 	i2c->state = code;  in xiic_wakeup()
348 	wake_up(&i2c->wait);  in xiic_wakeup()
362 	mutex_lock(&i2c->lock);  in xiic_process()
367 	dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",  in xiic_process()
369 	dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",  in xiic_process()
371 		i2c->tx_msg, i2c->nmsgs);  in xiic_process()
379 		 * Transmit error _OR_ RX completed  in xiic_process()
384 		dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);  in xiic_process()
392 		if (i2c->rx_msg)  in xiic_process()
394 		if (i2c->tx_msg)  in xiic_process()
398 		/* Receive register/FIFO is full */  in xiic_process()
401 		if (!i2c->rx_msg) {  in xiic_process()
402 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
403 				"%s unexpected RX IRQ\n", __func__);  in xiic_process()
411 			i2c->rx_msg = NULL;  in xiic_process()
413 			/* also clear TX error if there (RX complete) */  in xiic_process()
416 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
418 				__func__, i2c->nmsgs);  in xiic_process()
424 			if (i2c->nmsgs > 1) {  in xiic_process()
425 				i2c->nmsgs--;  in xiic_process()
426 				i2c->tx_msg++;  in xiic_process()
427 				dev_dbg(i2c->adap.dev.parent,  in xiic_process()
441 		if (!i2c->tx_msg)  in xiic_process()
444 		if ((i2c->nmsgs == 1) && !i2c->rx_msg &&  in xiic_process()
451 		/* Transmit register/FIFO is empty or ½ empty */  in xiic_process()
456 		if (!i2c->tx_msg) {  in xiic_process()
457 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
464 		/* current message sent and there is space in the fifo */  in xiic_process()
466 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
468 				__func__, i2c->nmsgs);  in xiic_process()
469 			if (i2c->nmsgs > 1) {  in xiic_process()
470 				i2c->nmsgs--;  in xiic_process()
471 				i2c->tx_msg++;  in xiic_process()
476 				dev_dbg(i2c->adap.dev.parent,  in xiic_process()
480 		} else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))  in xiic_process()
487 	dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);  in xiic_process()
490 	mutex_unlock(&i2c->lock);  in xiic_process()
498 	return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;  in xiic_bus_busy()
506 	if (i2c->tx_msg)  in xiic_busy()
507 		return -EBUSY;  in xiic_busy()
514 	while (err && tries--) {  in xiic_busy()
525 	struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;  in xiic_start_recv()
528 	/* Clear and enable Rx full interrupt. */  in xiic_start_recv()
535 	 * we can check if ERROR and RX full is set at the same time  in xiic_start_recv()
537 	rx_watermark = msg->len;  in xiic_start_recv()
540 	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);  in xiic_start_recv()
543 	if (!(msg->flags & I2C_M_NOSTART))  in xiic_start_recv()
551 		msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));  in xiic_start_recv()
554 	if (i2c->nmsgs == 1)  in xiic_start_recv()
559 	i2c->tx_pos = msg->len;  in xiic_start_recv()
564 	struct i2c_msg *msg = i2c->tx_msg;  in xiic_start_send()
568 	dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",  in xiic_start_send()
569 		__func__, msg, msg->len);  in xiic_start_send()
570 	dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",  in xiic_start_send()
574 	if (!(msg->flags & I2C_M_NOSTART)) {  in xiic_start_send()
578 		if ((i2c->nmsgs == 1) && msg->len == 0)  in xiic_start_send()
579 			/* no data and last message -> add STOP */  in xiic_start_send()
601 	dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);  in xiic_isr()
616 	dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",  in __xiic_start_xfer()
617 		__func__, i2c->tx_msg, fifo_space);  in __xiic_start_xfer()
619 	if (!i2c->tx_msg)  in __xiic_start_xfer()
622 	i2c->rx_pos = 0;  in __xiic_start_xfer()
623 	i2c->tx_pos = 0;  in __xiic_start_xfer()
624 	i2c->state = STATE_START;  in __xiic_start_xfer()
625 	while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {  in __xiic_start_xfer()
627 			i2c->nmsgs--;  in __xiic_start_xfer()
628 			i2c->tx_msg++;  in __xiic_start_xfer()
629 			i2c->tx_pos = 0;  in __xiic_start_xfer()
633 		if (i2c->tx_msg->flags & I2C_M_RD) {  in __xiic_start_xfer()
634 			/* we dont date putting several reads in the FIFO */  in __xiic_start_xfer()
649 	 * put into the FIFO, also enable the half empty interrupt  in __xiic_start_xfer()
651 	if (i2c->nmsgs > 1 || xiic_tx_space(i2c))  in __xiic_start_xfer()
658 	mutex_lock(&i2c->lock);  in xiic_start_xfer()
661 	mutex_unlock(&i2c->lock);  in xiic_start_xfer()
669 	dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,  in xiic_xfer()
672 	err = pm_runtime_get_sync(i2c->dev);  in xiic_xfer()
680 	i2c->tx_msg = msgs;  in xiic_xfer()
681 	i2c->nmsgs = num;  in xiic_xfer()
685 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||  in xiic_xfer()
686 		(i2c->state == STATE_DONE), HZ)) {  in xiic_xfer()
687 		err = (i2c->state == STATE_DONE) ? num : -EIO;  in xiic_xfer()
690 		i2c->tx_msg = NULL;  in xiic_xfer()
691 		i2c->rx_msg = NULL;  in xiic_xfer()
692 		i2c->nmsgs = 0;  in xiic_xfer()
693 		err = -ETIMEDOUT;  in xiic_xfer()
697 	pm_runtime_mark_last_busy(i2c->dev);  in xiic_xfer()
698 	pm_runtime_put_autosuspend(i2c->dev);  in xiic_xfer()
734 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);  in xiic_i2c_probe()
736 		return -ENOMEM;  in xiic_i2c_probe()
739 	i2c->base = devm_ioremap_resource(&pdev->dev, res);  in xiic_i2c_probe()
740 	if (IS_ERR(i2c->base))  in xiic_i2c_probe()
741 		return PTR_ERR(i2c->base);  in xiic_i2c_probe()
747 	pdata = dev_get_platdata(&pdev->dev);  in xiic_i2c_probe()
751 	i2c->adap = xiic_adapter;  in xiic_i2c_probe()
752 	i2c_set_adapdata(&i2c->adap, i2c);  in xiic_i2c_probe()
753 	i2c->adap.dev.parent = &pdev->dev;  in xiic_i2c_probe()
754 	i2c->adap.dev.of_node = pdev->dev.of_node;  in xiic_i2c_probe()
756 	mutex_init(&i2c->lock);  in xiic_i2c_probe()
757 	init_waitqueue_head(&i2c->wait);  in xiic_i2c_probe()
759 	i2c->clk = devm_clk_get(&pdev->dev, NULL);  in xiic_i2c_probe()
760 	if (IS_ERR(i2c->clk)) {  in xiic_i2c_probe()
761 		dev_err(&pdev->dev, "input clock not found.\n");  in xiic_i2c_probe()
762 		return PTR_ERR(i2c->clk);  in xiic_i2c_probe()
764 	ret = clk_prepare_enable(i2c->clk);  in xiic_i2c_probe()
766 		dev_err(&pdev->dev, "Unable to enable clock.\n");  in xiic_i2c_probe()
769 	i2c->dev = &pdev->dev;  in xiic_i2c_probe()
770 	pm_runtime_enable(i2c->dev);  in xiic_i2c_probe()
771 	pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);  in xiic_i2c_probe()
772 	pm_runtime_use_autosuspend(i2c->dev);  in xiic_i2c_probe()
773 	pm_runtime_set_active(i2c->dev);  in xiic_i2c_probe()
774 	ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,  in xiic_i2c_probe()
776 					pdev->name, i2c);  in xiic_i2c_probe()
779 		dev_err(&pdev->dev, "Cannot claim IRQ\n");  in xiic_i2c_probe()
785 	 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not  in xiic_i2c_probe()
788 	i2c->endianness = LITTLE;  in xiic_i2c_probe()
793 		i2c->endianness = BIG;  in xiic_i2c_probe()
798 	ret = i2c_add_adapter(&i2c->adap);  in xiic_i2c_probe()
806 		for (i = 0; i < pdata->num_devices; i++)  in xiic_i2c_probe()
807 			i2c_new_device(&i2c->adap, pdata->devices + i);  in xiic_i2c_probe()
813 	pm_runtime_set_suspended(&pdev->dev);  in xiic_i2c_probe()
814 	pm_runtime_disable(&pdev->dev);  in xiic_i2c_probe()
815 	clk_disable_unprepare(i2c->clk);  in xiic_i2c_probe()
825 	i2c_del_adapter(&i2c->adap);  in xiic_i2c_remove()
827 	ret = clk_prepare_enable(i2c->clk);  in xiic_i2c_remove()
829 		dev_err(&pdev->dev, "Unable to enable clock.\n");  in xiic_i2c_remove()
833 	clk_disable_unprepare(i2c->clk);  in xiic_i2c_remove()
834 	pm_runtime_disable(&pdev->dev);  in xiic_i2c_remove()
841 	{ .compatible = "xlnx,xps-iic-2.00.a", },
851 	clk_disable(i2c->clk);  in xiic_i2c_runtime_suspend()
861 	ret = clk_enable(i2c->clk);  in xiic_i2c_runtime_resume()
886 MODULE_AUTHOR("info@mocean-labs.com");