Lines Matching full:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
164 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) argument
165 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) argument
167 static void xiic_start_xfer(struct xiic_i2c *i2c);
168 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) in xiic_setreg8() argument
180 if (i2c->endianness == LITTLE) in xiic_setreg8()
181 iowrite8(value, i2c->base + reg); in xiic_setreg8()
183 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
186 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) in xiic_getreg8() argument
190 if (i2c->endianness == LITTLE) in xiic_getreg8()
191 ret = ioread8(i2c->base + reg); in xiic_getreg8()
193 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
197 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) in xiic_setreg16() argument
199 if (i2c->endianness == LITTLE) in xiic_setreg16()
200 iowrite16(value, i2c->base + reg); in xiic_setreg16()
202 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
205 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) in xiic_setreg32() argument
207 if (i2c->endianness == LITTLE) in xiic_setreg32()
208 iowrite32(value, i2c->base + reg); in xiic_setreg32()
210 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
213 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) in xiic_getreg32() argument
217 if (i2c->endianness == LITTLE) in xiic_getreg32()
218 ret = ioread32(i2c->base + reg); in xiic_getreg32()
220 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
224 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) in xiic_irq_dis() argument
226 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_dis()
227 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); in xiic_irq_dis()
230 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_en() argument
232 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_en()
233 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); in xiic_irq_en()
236 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr() argument
238 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_irq_clr()
239 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); in xiic_irq_clr()
242 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr_en() argument
244 xiic_irq_clr(i2c, mask); in xiic_irq_clr_en()
245 xiic_irq_en(i2c, mask); in xiic_irq_clr_en()
248 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) in xiic_clear_rx_fifo() argument
251 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_clear_rx_fifo()
253 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) in xiic_clear_rx_fifo()
254 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_clear_rx_fifo()
257 static void xiic_reinit(struct xiic_i2c *i2c) in xiic_reinit() argument
259 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_reinit()
262 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
265 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_reinit()
268 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); in xiic_reinit()
271 xiic_clear_rx_fifo(i2c); in xiic_reinit()
274 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_reinit()
276 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); in xiic_reinit()
279 static void xiic_deinit(struct xiic_i2c *i2c) in xiic_deinit() argument
283 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_deinit()
286 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_deinit()
287 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); in xiic_deinit()
290 static void xiic_read_rx(struct xiic_i2c *i2c) in xiic_read_rx() argument
295 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; in xiic_read_rx()
297 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
299 __func__, bytes_in_fifo, xiic_rx_space(i2c), in xiic_read_rx()
300 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_read_rx()
301 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_read_rx()
303 if (bytes_in_fifo > xiic_rx_space(i2c)) in xiic_read_rx()
304 bytes_in_fifo = xiic_rx_space(i2c); in xiic_read_rx()
307 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
308 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_read_rx()
310 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, in xiic_read_rx()
311 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? in xiic_read_rx()
312 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); in xiic_read_rx()
315 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) in xiic_tx_fifo_space() argument
318 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
321 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) in xiic_fill_tx_fifo() argument
323 u8 fifo_space = xiic_tx_fifo_space(i2c); in xiic_fill_tx_fifo()
324 int len = xiic_tx_space(i2c); in xiic_fill_tx_fifo()
328 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
332 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
333 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { in xiic_fill_tx_fifo()
336 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
338 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_fill_tx_fifo()
342 static void xiic_wakeup(struct xiic_i2c *i2c, int code) in xiic_wakeup() argument
344 i2c->tx_msg = NULL; in xiic_wakeup()
345 i2c->rx_msg = NULL; in xiic_wakeup()
346 i2c->nmsgs = 0; in xiic_wakeup()
347 i2c->state = code; in xiic_wakeup()
348 wake_up(&i2c->wait); in xiic_wakeup()
353 struct xiic_i2c *i2c = dev_id; in xiic_process() local
362 mutex_lock(&i2c->lock); in xiic_process()
363 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_process()
364 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_process()
367 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
369 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
370 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_process()
371 i2c->tx_msg, i2c->nmsgs); in xiic_process()
384 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
390 xiic_reinit(i2c); in xiic_process()
392 if (i2c->rx_msg) in xiic_process()
393 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
394 if (i2c->tx_msg) in xiic_process()
395 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
401 if (!i2c->rx_msg) { in xiic_process()
402 dev_dbg(i2c->adap.dev.parent, in xiic_process()
404 xiic_clear_rx_fifo(i2c); in xiic_process()
408 xiic_read_rx(i2c); in xiic_process()
409 if (xiic_rx_space(i2c) == 0) { in xiic_process()
411 i2c->rx_msg = NULL; in xiic_process()
416 dev_dbg(i2c->adap.dev.parent, in xiic_process()
418 __func__, i2c->nmsgs); in xiic_process()
424 if (i2c->nmsgs > 1) { in xiic_process()
425 i2c->nmsgs--; in xiic_process()
426 i2c->tx_msg++; in xiic_process()
427 dev_dbg(i2c->adap.dev.parent, in xiic_process()
430 __xiic_start_xfer(i2c); in xiic_process()
439 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); in xiic_process()
441 if (!i2c->tx_msg) in xiic_process()
444 if ((i2c->nmsgs == 1) && !i2c->rx_msg && in xiic_process()
445 xiic_tx_space(i2c) == 0) in xiic_process()
446 xiic_wakeup(i2c, STATE_DONE); in xiic_process()
448 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
456 if (!i2c->tx_msg) { in xiic_process()
457 dev_dbg(i2c->adap.dev.parent, in xiic_process()
462 xiic_fill_tx_fifo(i2c); in xiic_process()
465 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { in xiic_process()
466 dev_dbg(i2c->adap.dev.parent, in xiic_process()
468 __func__, i2c->nmsgs); in xiic_process()
469 if (i2c->nmsgs > 1) { in xiic_process()
470 i2c->nmsgs--; in xiic_process()
471 i2c->tx_msg++; in xiic_process()
472 __xiic_start_xfer(i2c); in xiic_process()
474 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
476 dev_dbg(i2c->adap.dev.parent, in xiic_process()
480 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) in xiic_process()
484 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
487 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
489 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
490 mutex_unlock(&i2c->lock); in xiic_process()
494 static int xiic_bus_busy(struct xiic_i2c *i2c) in xiic_bus_busy() argument
496 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_bus_busy()
501 static int xiic_busy(struct xiic_i2c *i2c) in xiic_busy() argument
506 if (i2c->tx_msg) in xiic_busy()
513 err = xiic_bus_busy(i2c); in xiic_busy()
516 err = xiic_bus_busy(i2c); in xiic_busy()
522 static void xiic_start_recv(struct xiic_i2c *i2c) in xiic_start_recv() argument
525 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
529 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); in xiic_start_recv()
540 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); in xiic_start_recv()
545 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
548 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
550 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
551 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); in xiic_start_recv()
554 if (i2c->nmsgs == 1) in xiic_start_recv()
556 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
559 i2c->tx_pos = msg->len; in xiic_start_recv()
562 static void xiic_start_send(struct xiic_i2c *i2c) in xiic_start_send() argument
564 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
566 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); in xiic_start_send()
568 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
570 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
571 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_send()
572 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_send()
578 if ((i2c->nmsgs == 1) && msg->len == 0) in xiic_start_send()
582 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
585 xiic_fill_tx_fifo(i2c); in xiic_start_send()
588 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | in xiic_start_send()
594 struct xiic_i2c *i2c = dev_id; in xiic_isr() local
601 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); in xiic_isr()
603 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_isr()
604 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_isr()
612 static void __xiic_start_xfer(struct xiic_i2c *i2c) in __xiic_start_xfer() argument
615 int fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
616 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
617 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
619 if (!i2c->tx_msg) in __xiic_start_xfer()
622 i2c->rx_pos = 0; in __xiic_start_xfer()
623 i2c->tx_pos = 0; in __xiic_start_xfer()
624 i2c->state = STATE_START; in __xiic_start_xfer()
625 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { in __xiic_start_xfer()
627 i2c->nmsgs--; in __xiic_start_xfer()
628 i2c->tx_msg++; in __xiic_start_xfer()
629 i2c->tx_pos = 0; in __xiic_start_xfer()
633 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
635 xiic_start_recv(i2c); in __xiic_start_xfer()
638 xiic_start_send(i2c); in __xiic_start_xfer()
639 if (xiic_tx_space(i2c) != 0) { in __xiic_start_xfer()
645 fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
651 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) in __xiic_start_xfer()
652 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); in __xiic_start_xfer()
656 static void xiic_start_xfer(struct xiic_i2c *i2c) in xiic_start_xfer() argument
658 mutex_lock(&i2c->lock); in xiic_start_xfer()
659 xiic_reinit(i2c); in xiic_start_xfer()
660 __xiic_start_xfer(i2c); in xiic_start_xfer()
661 mutex_unlock(&i2c->lock); in xiic_start_xfer()
666 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer() local
670 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); in xiic_xfer()
672 err = pm_runtime_get_sync(i2c->dev); in xiic_xfer()
676 err = xiic_busy(i2c); in xiic_xfer()
680 i2c->tx_msg = msgs; in xiic_xfer()
681 i2c->nmsgs = num; in xiic_xfer()
683 xiic_start_xfer(i2c); in xiic_xfer()
685 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || in xiic_xfer()
686 (i2c->state == STATE_DONE), HZ)) { in xiic_xfer()
687 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
690 i2c->tx_msg = NULL; in xiic_xfer()
691 i2c->rx_msg = NULL; in xiic_xfer()
692 i2c->nmsgs = 0; in xiic_xfer()
697 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
698 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
727 struct xiic_i2c *i2c; in xiic_i2c_probe() local
734 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
735 if (!i2c) in xiic_i2c_probe()
739 i2c->base = devm_ioremap_resource(&pdev->dev, res); in xiic_i2c_probe()
740 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
741 return PTR_ERR(i2c->base); in xiic_i2c_probe()
750 platform_set_drvdata(pdev, i2c); in xiic_i2c_probe()
751 i2c->adap = xiic_adapter; in xiic_i2c_probe()
752 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
753 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
754 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
756 mutex_init(&i2c->lock); in xiic_i2c_probe()
757 init_waitqueue_head(&i2c->wait); in xiic_i2c_probe()
759 i2c->clk = devm_clk_get(&pdev->dev, NULL); in xiic_i2c_probe()
760 if (IS_ERR(i2c->clk)) { in xiic_i2c_probe()
762 return PTR_ERR(i2c->clk); in xiic_i2c_probe()
764 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_probe()
769 i2c->dev = &pdev->dev; in xiic_i2c_probe()
770 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
771 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
772 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
773 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
776 pdev->name, i2c); in xiic_i2c_probe()
788 i2c->endianness = LITTLE; in xiic_i2c_probe()
789 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_i2c_probe()
791 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); in xiic_i2c_probe()
793 i2c->endianness = BIG; in xiic_i2c_probe()
795 xiic_reinit(i2c); in xiic_i2c_probe()
797 /* add i2c adapter to i2c tree */ in xiic_i2c_probe()
798 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
800 xiic_deinit(i2c); in xiic_i2c_probe()
807 i2c_new_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
815 clk_disable_unprepare(i2c->clk); in xiic_i2c_probe()
821 struct xiic_i2c *i2c = platform_get_drvdata(pdev); in xiic_i2c_remove() local
825 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
827 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_remove()
832 xiic_deinit(i2c); in xiic_i2c_remove()
833 clk_disable_unprepare(i2c->clk); in xiic_i2c_remove()
849 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_suspend() local
851 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
858 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_resume() local
861 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
887 MODULE_DESCRIPTION("Xilinx I2C bus driver");