Lines Matching refs:i2c_dev
284 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, in dvc_writel() argument
287 writel(val, i2c_dev->base + reg); in dvc_writel()
290 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) in dvc_readl() argument
292 return readl(i2c_dev->base + reg); in dvc_readl()
299 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, in tegra_i2c_reg_addr() argument
302 if (i2c_dev->is_dvc) in tegra_i2c_reg_addr()
307 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, in i2c_writel() argument
310 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
314 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
317 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) in i2c_readl() argument
319 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
322 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, in i2c_writesl() argument
325 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
328 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, in i2c_readsl() argument
331 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
334 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) in tegra_i2c_mask_irq() argument
338 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; in tegra_i2c_mask_irq()
339 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); in tegra_i2c_mask_irq()
342 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) in tegra_i2c_unmask_irq() argument
346 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; in tegra_i2c_unmask_irq()
347 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); in tegra_i2c_unmask_irq()
352 struct tegra_i2c_dev *i2c_dev = args; in tegra_i2c_dma_complete() local
354 complete(&i2c_dev->dma_complete); in tegra_i2c_dma_complete()
357 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) in tegra_i2c_dma_submit() argument
363 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); in tegra_i2c_dma_submit()
364 reinit_completion(&i2c_dev->dma_complete); in tegra_i2c_dma_submit()
365 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; in tegra_i2c_dma_submit()
366 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; in tegra_i2c_dma_submit()
367 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, in tegra_i2c_dma_submit()
371 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n"); in tegra_i2c_dma_submit()
376 dma_desc->callback_param = i2c_dev; in tegra_i2c_dma_submit()
382 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_release_dma() argument
384 if (i2c_dev->dma_buf) { in tegra_i2c_release_dma()
385 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, in tegra_i2c_release_dma()
386 i2c_dev->dma_buf, i2c_dev->dma_phys); in tegra_i2c_release_dma()
387 i2c_dev->dma_buf = NULL; in tegra_i2c_release_dma()
390 if (i2c_dev->tx_dma_chan) { in tegra_i2c_release_dma()
391 dma_release_channel(i2c_dev->tx_dma_chan); in tegra_i2c_release_dma()
392 i2c_dev->tx_dma_chan = NULL; in tegra_i2c_release_dma()
395 if (i2c_dev->rx_dma_chan) { in tegra_i2c_release_dma()
396 dma_release_channel(i2c_dev->rx_dma_chan); in tegra_i2c_release_dma()
397 i2c_dev->rx_dma_chan = NULL; in tegra_i2c_release_dma()
401 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_init_dma() argument
408 if (!i2c_dev->hw->has_apb_dma) in tegra_i2c_init_dma()
412 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n"); in tegra_i2c_init_dma()
416 chan = dma_request_slave_channel_reason(i2c_dev->dev, "rx"); in tegra_i2c_init_dma()
422 i2c_dev->rx_dma_chan = chan; in tegra_i2c_init_dma()
424 chan = dma_request_slave_channel_reason(i2c_dev->dev, "tx"); in tegra_i2c_init_dma()
430 i2c_dev->tx_dma_chan = chan; in tegra_i2c_init_dma()
432 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, in tegra_i2c_init_dma()
435 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n"); in tegra_i2c_init_dma()
440 i2c_dev->dma_buf = dma_buf; in tegra_i2c_init_dma()
441 i2c_dev->dma_phys = dma_phys; in tegra_i2c_init_dma()
445 tegra_i2c_release_dma(i2c_dev); in tegra_i2c_init_dma()
447 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); in tegra_i2c_init_dma()
448 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_init_dma()
455 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_flush_fifos() argument
461 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
471 val = i2c_readl(i2c_dev, offset); in tegra_i2c_flush_fifos()
473 i2c_writel(i2c_dev, val, offset); in tegra_i2c_flush_fifos()
475 while (i2c_readl(i2c_dev, offset) & mask) { in tegra_i2c_flush_fifos()
477 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); in tegra_i2c_flush_fifos()
485 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_empty_rx_fifo() argument
489 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
490 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
497 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) in tegra_i2c_empty_rx_fifo()
500 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
501 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); in tegra_i2c_empty_rx_fifo()
505 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); in tegra_i2c_empty_rx_fifo()
515 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); in tegra_i2c_empty_rx_fifo()
531 val = i2c_readl(i2c_dev, I2C_RX_FIFO); in tegra_i2c_empty_rx_fifo()
542 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
543 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
548 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_fill_tx_fifo() argument
552 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
553 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
556 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
557 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); in tegra_i2c_fill_tx_fifo()
561 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); in tegra_i2c_fill_tx_fifo()
583 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
584 i2c_dev->msg_buf = buf + in tegra_i2c_fill_tx_fifo()
588 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); in tegra_i2c_fill_tx_fifo()
608 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
609 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
612 i2c_writel(i2c_dev, val, I2C_TX_FIFO); in tegra_i2c_fill_tx_fifo()
625 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) in tegra_dvc_init() argument
629 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); in tegra_dvc_init()
632 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); in tegra_dvc_init()
634 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); in tegra_dvc_init()
636 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); in tegra_dvc_init()
641 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); in tegra_i2c_runtime_resume() local
644 ret = pinctrl_pm_select_default_state(i2c_dev->dev); in tegra_i2c_runtime_resume()
648 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_runtime_resume()
649 ret = clk_enable(i2c_dev->fast_clk); in tegra_i2c_runtime_resume()
651 dev_err(i2c_dev->dev, in tegra_i2c_runtime_resume()
657 ret = clk_enable(i2c_dev->div_clk); in tegra_i2c_runtime_resume()
659 dev_err(i2c_dev->dev, in tegra_i2c_runtime_resume()
661 clk_disable(i2c_dev->fast_clk); in tegra_i2c_runtime_resume()
670 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); in tegra_i2c_runtime_suspend() local
672 clk_disable(i2c_dev->div_clk); in tegra_i2c_runtime_suspend()
673 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_runtime_suspend()
674 clk_disable(i2c_dev->fast_clk); in tegra_i2c_runtime_suspend()
676 return pinctrl_pm_select_idle_state(i2c_dev->dev); in tegra_i2c_runtime_suspend()
679 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_wait_for_config_load() argument
686 if (i2c_dev->hw->has_config_load_reg) { in tegra_i2c_wait_for_config_load()
687 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); in tegra_i2c_wait_for_config_load()
688 addr = i2c_dev->base + reg_offset; in tegra_i2c_wait_for_config_load()
689 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); in tegra_i2c_wait_for_config_load()
699 dev_warn(i2c_dev->dev, in tegra_i2c_wait_for_config_load()
708 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) in tegra_i2c_init() argument
716 reset_control_assert(i2c_dev->rst); in tegra_i2c_init()
718 reset_control_deassert(i2c_dev->rst); in tegra_i2c_init()
720 if (i2c_dev->is_dvc) in tegra_i2c_init()
721 tegra_dvc_init(i2c_dev); in tegra_i2c_init()
726 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
729 i2c_writel(i2c_dev, val, I2C_CNFG); in tegra_i2c_init()
730 i2c_writel(i2c_dev, 0, I2C_INT_MASK); in tegra_i2c_init()
733 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; in tegra_i2c_init()
734 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << in tegra_i2c_init()
736 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); in tegra_i2c_init()
738 if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && in tegra_i2c_init()
739 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) { in tegra_i2c_init()
740 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; in tegra_i2c_init()
741 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
742 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; in tegra_i2c_init()
744 tlow = i2c_dev->hw->tlow_std_mode; in tegra_i2c_init()
745 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
746 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; in tegra_i2c_init()
749 if (i2c_dev->hw->has_interface_timing_reg) { in tegra_i2c_init()
751 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); in tegra_i2c_init()
758 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) in tegra_i2c_init()
759 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); in tegra_i2c_init()
763 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); in tegra_i2c_init()
764 err = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_init()
765 i2c_dev->bus_clk_rate * clk_multiplier); in tegra_i2c_init()
767 dev_err(i2c_dev->dev, in tegra_i2c_init()
773 if (!i2c_dev->is_dvc) { in tegra_i2c_init()
774 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); in tegra_i2c_init()
777 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); in tegra_i2c_init()
778 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); in tegra_i2c_init()
779 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); in tegra_i2c_init()
782 err = tegra_i2c_flush_fifos(i2c_dev); in tegra_i2c_init()
786 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
787 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); in tegra_i2c_init()
789 err = tegra_i2c_wait_for_config_load(i2c_dev); in tegra_i2c_init()
793 if (i2c_dev->irq_disabled) { in tegra_i2c_init()
794 i2c_dev->irq_disabled = false; in tegra_i2c_init()
795 enable_irq(i2c_dev->irq); in tegra_i2c_init()
801 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_disable_packet_mode() argument
811 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); in tegra_i2c_disable_packet_mode()
813 cnfg = i2c_readl(i2c_dev, I2C_CNFG); in tegra_i2c_disable_packet_mode()
815 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); in tegra_i2c_disable_packet_mode()
817 return tegra_i2c_wait_for_config_load(i2c_dev); in tegra_i2c_disable_packet_mode()
824 struct tegra_i2c_dev *i2c_dev = dev_id; in tegra_i2c_isr() local
826 status = i2c_readl(i2c_dev, I2C_INT_STATUS); in tegra_i2c_isr()
828 spin_lock(&i2c_dev->xfer_lock); in tegra_i2c_isr()
830 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", in tegra_i2c_isr()
831 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), in tegra_i2c_isr()
832 i2c_readl(i2c_dev, I2C_STATUS), in tegra_i2c_isr()
833 i2c_readl(i2c_dev, I2C_CNFG)); in tegra_i2c_isr()
834 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
836 if (!i2c_dev->irq_disabled) { in tegra_i2c_isr()
837 disable_irq_nosync(i2c_dev->irq); in tegra_i2c_isr()
838 i2c_dev->irq_disabled = true; in tegra_i2c_isr()
844 tegra_i2c_disable_packet_mode(i2c_dev); in tegra_i2c_isr()
846 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
848 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
856 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) in tegra_i2c_isr()
859 if (!i2c_dev->is_curr_dma_xfer) { in tegra_i2c_isr()
860 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
861 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { in tegra_i2c_isr()
867 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; in tegra_i2c_isr()
872 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
873 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
874 tegra_i2c_fill_tx_fifo(i2c_dev); in tegra_i2c_isr()
876 tegra_i2c_mask_irq(i2c_dev, in tegra_i2c_isr()
881 i2c_writel(i2c_dev, status, I2C_INT_STATUS); in tegra_i2c_isr()
882 if (i2c_dev->is_dvc) in tegra_i2c_isr()
883 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); in tegra_i2c_isr()
893 if (i2c_dev->is_curr_dma_xfer) in tegra_i2c_isr()
894 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_isr()
899 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { in tegra_i2c_isr()
900 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
903 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
908 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | in tegra_i2c_isr()
911 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_isr()
912 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); in tegra_i2c_isr()
913 i2c_writel(i2c_dev, status, I2C_INT_STATUS); in tegra_i2c_isr()
914 if (i2c_dev->is_dvc) in tegra_i2c_isr()
915 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); in tegra_i2c_isr()
917 if (i2c_dev->is_curr_dma_xfer) { in tegra_i2c_isr()
918 if (i2c_dev->msg_read) in tegra_i2c_isr()
919 dmaengine_terminate_async(i2c_dev->rx_dma_chan); in tegra_i2c_isr()
921 dmaengine_terminate_async(i2c_dev->tx_dma_chan); in tegra_i2c_isr()
923 complete(&i2c_dev->dma_complete); in tegra_i2c_isr()
926 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
928 spin_unlock(&i2c_dev->xfer_lock); in tegra_i2c_isr()
932 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, in tegra_i2c_config_fifo_trig() argument
942 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
947 if (i2c_dev->is_curr_dma_xfer) { in tegra_i2c_config_fifo_trig()
955 if (i2c_dev->msg_read) { in tegra_i2c_config_fifo_trig()
956 chan = i2c_dev->rx_dma_chan; in tegra_i2c_config_fifo_trig()
957 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); in tegra_i2c_config_fifo_trig()
958 slv_config.src_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
962 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
967 chan = i2c_dev->tx_dma_chan; in tegra_i2c_config_fifo_trig()
968 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); in tegra_i2c_config_fifo_trig()
969 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
973 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
982 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n", in tegra_i2c_config_fifo_trig()
984 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_config_fifo_trig()
985 tegra_i2c_release_dma(i2c_dev); in tegra_i2c_config_fifo_trig()
986 i2c_dev->is_curr_dma_xfer = false; in tegra_i2c_config_fifo_trig()
992 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
999 i2c_writel(i2c_dev, val, reg); in tegra_i2c_config_fifo_trig()
1004 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); in tegra_i2c_issue_bus_clear() local
1009 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_issue_bus_clear()
1012 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); in tegra_i2c_issue_bus_clear()
1013 if (i2c_dev->hw->has_config_load_reg) { in tegra_i2c_issue_bus_clear()
1014 err = tegra_i2c_wait_for_config_load(i2c_dev); in tegra_i2c_issue_bus_clear()
1020 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); in tegra_i2c_issue_bus_clear()
1021 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); in tegra_i2c_issue_bus_clear()
1023 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, in tegra_i2c_issue_bus_clear()
1026 dev_err(i2c_dev->dev, "timed out for bus clear\n"); in tegra_i2c_issue_bus_clear()
1030 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); in tegra_i2c_issue_bus_clear()
1032 dev_err(i2c_dev->dev, in tegra_i2c_issue_bus_clear()
1040 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, in tegra_i2c_xfer_msg() argument
1054 tegra_i2c_flush_fifos(i2c_dev); in tegra_i2c_xfer_msg()
1056 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
1057 i2c_dev->msg_buf_remaining = msg->len; in tegra_i2c_xfer_msg()
1058 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
1059 i2c_dev->msg_read = (msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
1060 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
1062 if (i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1068 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_MAX_LEN) && in tegra_i2c_xfer_msg()
1069 i2c_dev->dma_buf; in tegra_i2c_xfer_msg()
1070 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); in tegra_i2c_xfer_msg()
1071 dma = i2c_dev->is_curr_dma_xfer; in tegra_i2c_xfer_msg()
1077 i2c_dev->bus_clk_rate); in tegra_i2c_xfer_msg()
1078 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); in tegra_i2c_xfer_msg()
1081 tegra_i2c_unmask_irq(i2c_dev, int_mask); in tegra_i2c_xfer_msg()
1083 if (i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1084 dma_sync_single_for_device(i2c_dev->dev, in tegra_i2c_xfer_msg()
1085 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1088 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); in tegra_i2c_xfer_msg()
1090 dev_err(i2c_dev->dev, in tegra_i2c_xfer_msg()
1097 dma_sync_single_for_cpu(i2c_dev->dev, in tegra_i2c_xfer_msg()
1098 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1101 buffer = i2c_dev->dma_buf; in tegra_i2c_xfer_msg()
1107 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | in tegra_i2c_xfer_msg()
1109 if (dma && !i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1112 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); in tegra_i2c_xfer_msg()
1115 if (dma && !i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1118 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); in tegra_i2c_xfer_msg()
1135 if (dma && !i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1138 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); in tegra_i2c_xfer_msg()
1140 if (!i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1143 dma_sync_single_for_device(i2c_dev->dev, in tegra_i2c_xfer_msg()
1144 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1147 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); in tegra_i2c_xfer_msg()
1149 dev_err(i2c_dev->dev, in tegra_i2c_xfer_msg()
1155 tegra_i2c_fill_tx_fifo(i2c_dev); in tegra_i2c_xfer_msg()
1159 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
1164 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
1168 tegra_i2c_unmask_irq(i2c_dev, int_mask); in tegra_i2c_xfer_msg()
1169 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", in tegra_i2c_xfer_msg()
1170 i2c_readl(i2c_dev, I2C_INT_MASK)); in tegra_i2c_xfer_msg()
1173 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); in tegra_i2c_xfer_msg()
1179 time_left = wait_for_completion_timeout(&i2c_dev->dma_complete, in tegra_i2c_xfer_msg()
1182 dev_err(i2c_dev->dev, "DMA transfer timeout\n"); in tegra_i2c_xfer_msg()
1183 dmaengine_terminate_sync(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1184 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1185 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1186 tegra_i2c_init(i2c_dev, true); in tegra_i2c_xfer_msg()
1190 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { in tegra_i2c_xfer_msg()
1191 dma_sync_single_for_cpu(i2c_dev->dev, in tegra_i2c_xfer_msg()
1192 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1195 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, in tegra_i2c_xfer_msg()
1199 if (i2c_dev->msg_err != I2C_ERR_NONE) in tegra_i2c_xfer_msg()
1200 dmaengine_synchronize(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1201 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1202 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1205 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
1207 tegra_i2c_mask_irq(i2c_dev, int_mask); in tegra_i2c_xfer_msg()
1210 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); in tegra_i2c_xfer_msg()
1212 tegra_i2c_init(i2c_dev, true); in tegra_i2c_xfer_msg()
1216 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
1217 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
1218 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
1220 i2c_dev->is_curr_dma_xfer = false; in tegra_i2c_xfer_msg()
1221 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) in tegra_i2c_xfer_msg()
1224 tegra_i2c_init(i2c_dev, true); in tegra_i2c_xfer_msg()
1226 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { in tegra_i2c_xfer_msg()
1227 if (!i2c_dev->is_multimaster_mode) in tegra_i2c_xfer_msg()
1228 return i2c_recover_bus(&i2c_dev->adapter); in tegra_i2c_xfer_msg()
1232 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_xfer_msg()
1244 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); in tegra_i2c_xfer() local
1248 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
1250 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
1263 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); in tegra_i2c_xfer()
1268 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
1275 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); in tegra_i2c_func() local
1279 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
1284 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) in tegra_i2c_parse_dt() argument
1286 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
1291 &i2c_dev->bus_clk_rate); in tegra_i2c_parse_dt()
1293 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ in tegra_i2c_parse_dt()
1296 i2c_dev->is_multimaster_mode = multi_mode; in tegra_i2c_parse_dt()
1511 struct tegra_i2c_dev *i2c_dev; in tegra_i2c_probe() local
1541 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
1542 if (!i2c_dev) in tegra_i2c_probe()
1545 i2c_dev->base = base; in tegra_i2c_probe()
1546 i2c_dev->base_phys = base_phys; in tegra_i2c_probe()
1547 i2c_dev->div_clk = div_clk; in tegra_i2c_probe()
1548 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
1549 i2c_dev->adapter.retries = 1; in tegra_i2c_probe()
1550 i2c_dev->adapter.timeout = 6 * HZ; in tegra_i2c_probe()
1551 i2c_dev->irq = irq; in tegra_i2c_probe()
1552 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
1553 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
1555 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); in tegra_i2c_probe()
1556 if (IS_ERR(i2c_dev->rst)) { in tegra_i2c_probe()
1558 return PTR_ERR(i2c_dev->rst); in tegra_i2c_probe()
1561 tegra_i2c_parse_dt(i2c_dev); in tegra_i2c_probe()
1563 i2c_dev->hw = of_device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1564 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, in tegra_i2c_probe()
1566 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1567 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len + in tegra_i2c_probe()
1569 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1570 init_completion(&i2c_dev->dma_complete); in tegra_i2c_probe()
1571 spin_lock_init(&i2c_dev->xfer_lock); in tegra_i2c_probe()
1573 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_probe()
1579 i2c_dev->fast_clk = fast_clk; in tegra_i2c_probe()
1582 platform_set_drvdata(pdev, i2c_dev); in tegra_i2c_probe()
1584 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_probe()
1585 ret = clk_prepare(i2c_dev->fast_clk); in tegra_i2c_probe()
1587 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); in tegra_i2c_probe()
1592 if (i2c_dev->bus_clk_rate > I2C_FAST_MODE && in tegra_i2c_probe()
1593 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) in tegra_i2c_probe()
1594 i2c_dev->clk_divisor_non_hs_mode = in tegra_i2c_probe()
1595 i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_probe()
1596 else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && in tegra_i2c_probe()
1597 i2c_dev->bus_clk_rate <= I2C_FAST_MODE) in tegra_i2c_probe()
1598 i2c_dev->clk_divisor_non_hs_mode = in tegra_i2c_probe()
1599 i2c_dev->hw->clk_divisor_fast_mode; in tegra_i2c_probe()
1601 i2c_dev->clk_divisor_non_hs_mode = in tegra_i2c_probe()
1602 i2c_dev->hw->clk_divisor_std_mode; in tegra_i2c_probe()
1604 ret = clk_prepare(i2c_dev->div_clk); in tegra_i2c_probe()
1606 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); in tegra_i2c_probe()
1614 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_probe()
1621 if (i2c_dev->is_multimaster_mode) { in tegra_i2c_probe()
1622 ret = clk_enable(i2c_dev->div_clk); in tegra_i2c_probe()
1624 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", in tegra_i2c_probe()
1630 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_probe()
1631 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; in tegra_i2c_probe()
1633 ret = tegra_i2c_init_dma(i2c_dev); in tegra_i2c_probe()
1637 ret = tegra_i2c_init(i2c_dev, false); in tegra_i2c_probe()
1643 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, in tegra_i2c_probe()
1644 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); in tegra_i2c_probe()
1646 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); in tegra_i2c_probe()
1650 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1651 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1652 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1653 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), in tegra_i2c_probe()
1654 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1655 i2c_dev->adapter.dev.parent = &pdev->dev; in tegra_i2c_probe()
1656 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1657 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; in tegra_i2c_probe()
1659 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1668 tegra_i2c_release_dma(i2c_dev); in tegra_i2c_probe()
1671 if (i2c_dev->is_multimaster_mode) in tegra_i2c_probe()
1672 clk_disable(i2c_dev->div_clk); in tegra_i2c_probe()
1680 clk_unprepare(i2c_dev->div_clk); in tegra_i2c_probe()
1683 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_probe()
1684 clk_unprepare(i2c_dev->fast_clk); in tegra_i2c_probe()
1691 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); in tegra_i2c_remove() local
1693 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1695 if (i2c_dev->is_multimaster_mode) in tegra_i2c_remove()
1696 clk_disable(i2c_dev->div_clk); in tegra_i2c_remove()
1702 clk_unprepare(i2c_dev->div_clk); in tegra_i2c_remove()
1703 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_remove()
1704 clk_unprepare(i2c_dev->fast_clk); in tegra_i2c_remove()
1706 tegra_i2c_release_dma(i2c_dev); in tegra_i2c_remove()
1712 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); in tegra_i2c_suspend() local
1714 i2c_mark_adapter_suspended(&i2c_dev->adapter); in tegra_i2c_suspend()
1721 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); in tegra_i2c_resume() local
1728 err = tegra_i2c_init(i2c_dev, false); in tegra_i2c_resume()
1736 i2c_mark_adapter_resumed(&i2c_dev->adapter); in tegra_i2c_resume()