Lines Matching refs:bus_clk_rate
270 u32 bus_clk_rate; member
738 if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && in tegra_i2c_init()
739 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) { in tegra_i2c_init()
765 i2c_dev->bus_clk_rate * clk_multiplier); in tegra_i2c_init()
811 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); in tegra_i2c_disable_packet_mode()
1077 i2c_dev->bus_clk_rate); in tegra_i2c_xfer_msg()
1291 &i2c_dev->bus_clk_rate); in tegra_i2c_parse_dt()
1293 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ in tegra_i2c_parse_dt()
1592 if (i2c_dev->bus_clk_rate > I2C_FAST_MODE && in tegra_i2c_probe()
1593 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) in tegra_i2c_probe()
1596 else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && in tegra_i2c_probe()
1597 i2c_dev->bus_clk_rate <= I2C_FAST_MODE) in tegra_i2c_probe()