Lines Matching refs:STM32F7_I2C_CR1
39 #define STM32F7_I2C_CR1 0x00 macro
373 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
626 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_dma_req()
655 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
658 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
660 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
739 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
786 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
854 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
872 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_xfer_msg()
1020 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_xfer_msg()
1034 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_rep_start()
1104 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_rep_start()
1188 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1193 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1213 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1737 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_reg_slave()