47 	comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);  in i2c_dw_set_timings_master()
197 	ic_con = dw_readl(dev, DW_IC_CON);  in i2c_dw_xfer_init()
226 	dw_readl(dev, DW_IC_ENABLE_STATUS);  in i2c_dw_xfer_init()
229 	dw_readl(dev, DW_IC_CLR_INTR);  in i2c_dw_xfer_init()
281 		tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);  in i2c_dw_xfer_msg()
282 		rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);  in i2c_dw_xfer_msg()
391 		rx_valid = dw_readl(dev, DW_IC_RXFLR);  in i2c_dw_read()
396 			*buf = dw_readl(dev, DW_IC_DATA_CMD);  in i2c_dw_read()
534 	stat = dw_readl(dev, DW_IC_INTR_STAT);  in i2c_dw_read_clear_intrbits()
544 		dw_readl(dev, DW_IC_CLR_RX_UNDER);  in i2c_dw_read_clear_intrbits()
546 		dw_readl(dev, DW_IC_CLR_RX_OVER);  in i2c_dw_read_clear_intrbits()
548 		dw_readl(dev, DW_IC_CLR_TX_OVER);  in i2c_dw_read_clear_intrbits()
550 		dw_readl(dev, DW_IC_CLR_RD_REQ);  in i2c_dw_read_clear_intrbits()
556 		dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);  in i2c_dw_read_clear_intrbits()
557 		dw_readl(dev, DW_IC_CLR_TX_ABRT);  in i2c_dw_read_clear_intrbits()
560 		dw_readl(dev, DW_IC_CLR_RX_DONE);  in i2c_dw_read_clear_intrbits()
562 		dw_readl(dev, DW_IC_CLR_ACTIVITY);  in i2c_dw_read_clear_intrbits()
564 		dw_readl(dev, DW_IC_CLR_STOP_DET);  in i2c_dw_read_clear_intrbits()
566 		dw_readl(dev, DW_IC_CLR_START_DET);  in i2c_dw_read_clear_intrbits()
568 		dw_readl(dev, DW_IC_CLR_GEN_CALL);  in i2c_dw_read_clear_intrbits()
611 		stat = dw_readl(dev, DW_IC_INTR_MASK);  in i2c_dw_irq_handler_master()
624 	enabled = dw_readl(dev, DW_IC_ENABLE);  in i2c_dw_isr()
625 	stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);  in i2c_dw_isr()