31 #define msc_dev(x) (&(x)->thdev->dev)  macro
682 		dev_info(msc_dev(msc), "MINTCTL ignores writes: no usable interrupts\n");  in intel_th_msu_init()
721 		dev_warn_ratelimited(msc_dev(win->msc),  in msc_win_set_lockout()
835 		dev_dbg(msc_dev(msc), "MSCnMWP: %08x/%08lx, wrap: %d\n",  in msc_disable()
852 	dev_dbg(msc_dev(msc), "MSCnNWSA: %08x\n",  in msc_disable()
856 	dev_dbg(msc_dev(msc), "MSCnSTS: %08x\n", reg);  in msc_disable()
929 	ret = dma_map_sg(msc_dev(msc)->parent->parent, msc->single_sgt.sgl, 1,  in msc_buffer_contig_alloc()
958 	dma_unmap_sg(msc_dev(msc)->parent->parent, msc->single_sgt.sgl,  in msc_buffer_contig_free()
1000 		block = dma_alloc_coherent(msc_dev(win->msc)->parent->parent,  in __msc_buffer_win_alloc()
1013 		dma_free_coherent(msc_dev(win->msc)->parent->parent, PAGE_SIZE,  in __msc_buffer_win_alloc()
1126 		dma_free_coherent(msc_dev(win->msc)->parent->parent, PAGE_SIZE,  in __msc_buffer_win_free()
1660 		dev_dbg(msc_dev(msc), "timeout waiting for MSC0 PLE\n");  in intel_th_msc_wait_empty()