173 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))  macro
246 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);  in vc4_vec_ntsc_mode_set()
247 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_ntsc_mode_set()
252 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);  in vc4_vec_ntsc_j_mode_set()
253 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_ntsc_j_mode_set()
265 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);  in vc4_vec_pal_mode_set()
266 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_pal_mode_set()
271 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);  in vc4_vec_pal_m_mode_set()
272 	VEC_WRITE(VEC_CONFIG1,  in vc4_vec_pal_m_mode_set()
274 	VEC_WRITE(VEC_FREQ3_2, 0x223b);  in vc4_vec_pal_m_mode_set()
275 	VEC_WRITE(VEC_FREQ1_0, 0x61d1);  in vc4_vec_pal_m_mode_set()
387 	VEC_WRITE(VEC_CFG, 0);  in vc4_vec_encoder_disable()
388 	VEC_WRITE(VEC_DAC_MISC,  in vc4_vec_encoder_disable()
435 	VEC_WRITE(VEC_WSE_RESET, 1);  in vc4_vec_encoder_enable()
436 	VEC_WRITE(VEC_SOFT_RESET, 1);  in vc4_vec_encoder_enable()
439 	VEC_WRITE(VEC_WSE_CONTROL, 0);  in vc4_vec_encoder_enable()
447 	VEC_WRITE(VEC_SCHPH, 0x28);  in vc4_vec_encoder_enable()
452 	VEC_WRITE(VEC_CLMP0_START, 0xac);  in vc4_vec_encoder_enable()
453 	VEC_WRITE(VEC_CLMP0_END, 0xec);  in vc4_vec_encoder_enable()
454 	VEC_WRITE(VEC_CONFIG2,  in vc4_vec_encoder_enable()
456 	VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);  in vc4_vec_encoder_enable()
457 	VEC_WRITE(VEC_DAC_CONFIG,  in vc4_vec_encoder_enable()
463 	VEC_WRITE(VEC_MASK0, 0);  in vc4_vec_encoder_enable()
467 	VEC_WRITE(VEC_DAC_MISC,  in vc4_vec_encoder_enable()
469 	VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);  in vc4_vec_encoder_enable()