Lines Matching refs:tilcdc_write
106 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, in tilcdc_crtc_load_palette()
108 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, in tilcdc_crtc_load_palette()
121 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA); in tilcdc_crtc_load_palette()
137 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA); in tilcdc_crtc_load_palette()
153 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, in tilcdc_crtc_enable_irqs()
172 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, in tilcdc_crtc_disable_irqs()
259 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | in tilcdc_crtc_set_clk()
313 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); in tilcdc_crtc_set_mode()
342 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); in tilcdc_crtc_set_mode()
350 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); in tilcdc_crtc_set_mode()
356 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); in tilcdc_crtc_set_mode()
400 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); in tilcdc_crtc_set_mode()
688 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE); in tilcdc_crtc_reset()
925 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, in tilcdc_crtc_irq()
949 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, in tilcdc_crtc_irq()
970 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); in tilcdc_crtc_irq()