Lines Matching refs:tx_pu_value
43 u8 tx_pu_value; member
63 .tx_pu_value = 0x10,
78 .tx_pu_value = 0x40,
93 .tx_pu_value = 0x66,
108 .tx_pu_value = 0x66,
123 .tx_pu_value = 0x66,
142 .tx_pu_value = 0x40,
157 .tx_pu_value = 0x66,
172 .tx_pu_value = 0x66,
187 .tx_pu_value = 0x66,
207 .tx_pu_value = 0,
222 .tx_pu_value = 0,
237 .tx_pu_value = 0x66 /* 0 */,
252 .tx_pu_value = 64,
267 .tx_pu_value = 96,
286 .tx_pu_value = 0,
301 .tx_pu_value = 0,
316 .tx_pu_value = 0x66 /* 0 */,
331 .tx_pu_value = 64,
346 .tx_pu_value = 96,
2690 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()