Lines Matching refs:tegra_sor_readl
474 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() function
527 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
630 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
636 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
643 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
667 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
724 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
729 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
739 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
754 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
761 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
769 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
787 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
803 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
810 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1000 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1005 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1024 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1029 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1043 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1129 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1137 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1146 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1152 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1160 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1178 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1186 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1203 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1216 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1226 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1232 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1236 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1253 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1279 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1283 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1287 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1296 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1445 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1722 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1727 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1732 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1740 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1750 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1757 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1767 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1773 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1782 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1794 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1801 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1806 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1813 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1831 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1850 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1861 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1869 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1877 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1892 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1911 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1916 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_edp_enable()
2111 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2133 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2197 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2209 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_hdmi_audio_enable()
2272 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2283 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2309 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2337 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2456 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2462 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2466 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2471 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2477 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2484 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2502 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2509 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2527 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2532 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2628 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2634 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2646 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2656 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2664 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2687 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2693 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2699 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2739 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2749 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2755 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2765 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
3224 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3228 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()