364 	unsigned int pll0;  member
1232 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_power_down()
1234 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_power_down()
1738 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1778 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1780 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1801 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1804 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
2466 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2469 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2646 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2653 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
3038 	.pll0 = 0x17,
3063 	.pll0 = 0x17,
3107 	.pll0 = 0x163,
3149 	.pll0 = 0x169,