67 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,  in tegra_dpaux_readl()  argument
70 	u32 value = readl(dpaux->regs + (offset << 2));  in tegra_dpaux_readl()
72 	trace_dpaux_readl(dpaux->dev, offset, value);  in tegra_dpaux_readl()
77 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,  in tegra_dpaux_writel()  argument
80 	trace_dpaux_writel(dpaux->dev, offset, value);  in tegra_dpaux_writel()
81 	writel(value, dpaux->regs + (offset << 2));  in tegra_dpaux_writel()
84 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,  in tegra_dpaux_write_fifo()  argument
96 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));  in tegra_dpaux_write_fifo()
100 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,  in tegra_dpaux_read_fifo()  argument
109 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));  in tegra_dpaux_read_fifo()
120 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in tegra_dpaux_transfer()  local
186 	tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);  in tegra_dpaux_transfer()
187 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
190 		tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);  in tegra_dpaux_transfer()
195 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
197 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
199 	status = wait_for_completion_timeout(&dpaux->complete, timeout);  in tegra_dpaux_transfer()
204 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
205 	tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
244 			tegra_dpaux_read_fifo(dpaux, msg->buffer, count);  in tegra_dpaux_transfer()
254 	struct tegra_dpaux *dpaux = work_to_dpaux(work);  in tegra_dpaux_hotplug()  local
256 	if (dpaux->output)  in tegra_dpaux_hotplug()
257 		drm_helper_hpd_irq_event(dpaux->output->connector.dev);  in tegra_dpaux_hotplug()
262 	struct tegra_dpaux *dpaux = data;  in tegra_dpaux_irq()  local
267 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
268 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
271 		schedule_work(&dpaux->work);  in tegra_dpaux_irq()
278 		complete(&dpaux->complete);  in tegra_dpaux_irq()
289 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)  in tegra_dpaux_pad_power_down()  argument
291 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_down()
295 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_down()
298 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)  in tegra_dpaux_pad_power_up()  argument
300 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_up()
304 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_up()
307 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)  in tegra_dpaux_pad_config()  argument
330 		tegra_dpaux_pad_power_down(dpaux);  in tegra_dpaux_pad_config()
337 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_pad_config()
338 	tegra_dpaux_pad_power_up(dpaux);  in tegra_dpaux_pad_config()
415 	struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);  in tegra_dpaux_set_mux()  local
417 	return tegra_dpaux_pad_config(dpaux, function);  in tegra_dpaux_set_mux()
430 	struct tegra_dpaux *dpaux;  in tegra_dpaux_probe()  local
435 	dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);  in tegra_dpaux_probe()
436 	if (!dpaux)  in tegra_dpaux_probe()
439 	INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);  in tegra_dpaux_probe()
440 	init_completion(&dpaux->complete);  in tegra_dpaux_probe()
441 	INIT_LIST_HEAD(&dpaux->list);  in tegra_dpaux_probe()
442 	dpaux->dev = &pdev->dev;  in tegra_dpaux_probe()
445 	dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);  in tegra_dpaux_probe()
446 	if (IS_ERR(dpaux->regs))  in tegra_dpaux_probe()
447 		return PTR_ERR(dpaux->regs);  in tegra_dpaux_probe()
449 	dpaux->irq = platform_get_irq(pdev, 0);  in tegra_dpaux_probe()
450 	if (dpaux->irq < 0) {  in tegra_dpaux_probe()
456 		dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");  in tegra_dpaux_probe()
457 		if (IS_ERR(dpaux->rst)) {  in tegra_dpaux_probe()
460 				PTR_ERR(dpaux->rst));  in tegra_dpaux_probe()
461 			return PTR_ERR(dpaux->rst);  in tegra_dpaux_probe()
465 	dpaux->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_dpaux_probe()
466 	if (IS_ERR(dpaux->clk)) {  in tegra_dpaux_probe()
468 			PTR_ERR(dpaux->clk));  in tegra_dpaux_probe()
469 		return PTR_ERR(dpaux->clk);  in tegra_dpaux_probe()
472 	dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");  in tegra_dpaux_probe()
473 	if (IS_ERR(dpaux->clk_parent)) {  in tegra_dpaux_probe()
475 			PTR_ERR(dpaux->clk_parent));  in tegra_dpaux_probe()
476 		return PTR_ERR(dpaux->clk_parent);  in tegra_dpaux_probe()
479 	err = clk_set_rate(dpaux->clk_parent, 270000000);  in tegra_dpaux_probe()
486 	dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");  in tegra_dpaux_probe()
487 	if (IS_ERR(dpaux->vdd)) {  in tegra_dpaux_probe()
488 		if (PTR_ERR(dpaux->vdd) != -ENODEV) {  in tegra_dpaux_probe()
489 			if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)  in tegra_dpaux_probe()
492 					PTR_ERR(dpaux->vdd));  in tegra_dpaux_probe()
494 			return PTR_ERR(dpaux->vdd);  in tegra_dpaux_probe()
498 	platform_set_drvdata(pdev, dpaux);  in tegra_dpaux_probe()
502 	err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,  in tegra_dpaux_probe()
503 			       dev_name(dpaux->dev), dpaux);  in tegra_dpaux_probe()
505 		dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",  in tegra_dpaux_probe()
506 			dpaux->irq, err);  in tegra_dpaux_probe()
510 	disable_irq(dpaux->irq);  in tegra_dpaux_probe()
512 	dpaux->aux.transfer = tegra_dpaux_transfer;  in tegra_dpaux_probe()
513 	dpaux->aux.dev = &pdev->dev;  in tegra_dpaux_probe()
515 	err = drm_dp_aux_register(&dpaux->aux);  in tegra_dpaux_probe()
527 	err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);  in tegra_dpaux_probe()
532 	dpaux->desc.name = dev_name(&pdev->dev);  in tegra_dpaux_probe()
533 	dpaux->desc.pins = tegra_dpaux_pins;  in tegra_dpaux_probe()
534 	dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);  in tegra_dpaux_probe()
535 	dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;  in tegra_dpaux_probe()
536 	dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;  in tegra_dpaux_probe()
537 	dpaux->desc.owner = THIS_MODULE;  in tegra_dpaux_probe()
539 	dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);  in tegra_dpaux_probe()
540 	if (IS_ERR(dpaux->pinctrl)) {  in tegra_dpaux_probe()
542 		return PTR_ERR(dpaux->pinctrl);  in tegra_dpaux_probe()
548 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);  in tegra_dpaux_probe()
549 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_probe()
552 	list_add_tail(&dpaux->list, &dpaux_list);  in tegra_dpaux_probe()
560 	struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);  in tegra_dpaux_remove()  local
562 	cancel_work_sync(&dpaux->work);  in tegra_dpaux_remove()
565 	tegra_dpaux_pad_power_down(dpaux);  in tegra_dpaux_remove()
570 	drm_dp_aux_unregister(&dpaux->aux);  in tegra_dpaux_remove()
573 	list_del(&dpaux->list);  in tegra_dpaux_remove()
582 	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);  in tegra_dpaux_suspend()  local
585 	if (dpaux->rst) {  in tegra_dpaux_suspend()
586 		err = reset_control_assert(dpaux->rst);  in tegra_dpaux_suspend()
595 	clk_disable_unprepare(dpaux->clk_parent);  in tegra_dpaux_suspend()
596 	clk_disable_unprepare(dpaux->clk);  in tegra_dpaux_suspend()
603 	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);  in tegra_dpaux_resume()  local
606 	err = clk_prepare_enable(dpaux->clk);  in tegra_dpaux_resume()
612 	err = clk_prepare_enable(dpaux->clk_parent);  in tegra_dpaux_resume()
620 	if (dpaux->rst) {  in tegra_dpaux_resume()
621 		err = reset_control_deassert(dpaux->rst);  in tegra_dpaux_resume()
633 	clk_disable_unprepare(dpaux->clk_parent);  in tegra_dpaux_resume()
635 	clk_disable_unprepare(dpaux->clk);  in tegra_dpaux_resume()
665 	struct tegra_dpaux *dpaux;  in drm_dp_aux_find_by_of_node()  local
669 	list_for_each_entry(dpaux, &dpaux_list, list)  in drm_dp_aux_find_by_of_node()
670 		if (np == dpaux->dev->of_node) {  in drm_dp_aux_find_by_of_node()
672 			return &dpaux->aux;  in drm_dp_aux_find_by_of_node()
682 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in drm_dp_aux_attach()  local
687 	dpaux->output = output;  in drm_dp_aux_attach()
689 	err = regulator_enable(dpaux->vdd);  in drm_dp_aux_attach()
700 			enable_irq(dpaux->irq);  in drm_dp_aux_attach()
712 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in drm_dp_aux_detach()  local
716 	disable_irq(dpaux->irq);  in drm_dp_aux_detach()
718 	err = regulator_disable(dpaux->vdd);  in drm_dp_aux_detach()
729 			dpaux->output = NULL;  in drm_dp_aux_detach()
741 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in drm_dp_aux_detect()  local
744 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in drm_dp_aux_detect()
754 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in drm_dp_aux_enable()  local
756 	return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);  in drm_dp_aux_enable()
761 	struct tegra_dpaux *dpaux = to_dpaux(aux);  in drm_dp_aux_disable()  local
763 	tegra_dpaux_pad_power_down(dpaux);  in drm_dp_aux_disable()