47 	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
49 	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
86 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));  in tegra_plane_writel()
116 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
117 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
873 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);  in tegra_cursor_atomic_update()
877 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);  in tegra_cursor_atomic_update()
883 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
892 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
896 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);  in tegra_cursor_atomic_update()
913 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
1456 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1465 	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1556 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
1568 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1593 		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);  in tegra_dc_set_timings()
1596 		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);  in tegra_dc_set_timings()
1601 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);  in tegra_dc_set_timings()
1605 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);  in tegra_dc_set_timings()
1609 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);  in tegra_dc_set_timings()
1612 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);  in tegra_dc_set_timings()
1678 		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);  in tegra_dc_commit_state()
1694 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1759 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_disable()
1797 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);  in tegra_crtc_atomic_enable()
1800 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);  in tegra_crtc_atomic_enable()
1806 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
1813 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
1817 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
1820 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
1822 		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_crtc_atomic_enable()
1826 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
1830 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
1835 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);  in tegra_crtc_atomic_enable()
1839 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);  in tegra_crtc_atomic_enable()
1843 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
1847 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
1851 		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);  in tegra_crtc_atomic_enable()
1853 		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);  in tegra_crtc_atomic_enable()
1865 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_atomic_enable()
1871 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_atomic_enable()
1877 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_enable()
1883 		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);  in tegra_crtc_atomic_enable()
1918 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
1922 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
1939 	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);  in tegra_dc_irq()