Lines Matching full:phy
134 struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_config_a83t() argument
137 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_hdmi_phy_config_a83t()
196 struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_config_h3() argument
264 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_hdmi_phy_config_h3()
274 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_hdmi_phy_config_h3()
300 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_config_h3()
304 * NOTE: We have to be careful not to overwrite PHY parent in sun8i_hdmi_phy_config_h3()
307 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
310 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, in sun8i_hdmi_phy_config_h3()
314 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG, in sun8i_hdmi_phy_config_h3()
316 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
322 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_hdmi_phy_config_h3()
327 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
332 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
336 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end); in sun8i_hdmi_phy_config_h3()
337 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init); in sun8i_hdmi_phy_config_h3()
338 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init); in sun8i_hdmi_phy_config_h3()
346 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; in sun8i_hdmi_phy_config() local
355 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_config()
358 if (phy->variant->has_phy_clk) in sun8i_hdmi_phy_config()
359 clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000); in sun8i_hdmi_phy_config()
361 return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000); in sun8i_hdmi_phy_config()
365 struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_disable_a83t() argument
370 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_hdmi_phy_disable_a83t()
375 struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_disable_h3() argument
377 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_disable_h3()
381 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0); in sun8i_hdmi_phy_disable_h3()
386 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; in sun8i_hdmi_phy_disable() local
388 phy->variant->phy_disable(hdmi, phy); in sun8i_hdmi_phy_disable()
399 static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_unlock() argument
402 regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG, in sun8i_hdmi_phy_unlock()
406 regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG, in sun8i_hdmi_phy_unlock()
410 static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy) in sun50i_hdmi_phy_init_h6() argument
412 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun50i_hdmi_phy_init_h6()
416 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun50i_hdmi_phy_init_h6()
420 static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_a83t() argument
422 sun8i_hdmi_phy_unlock(phy); in sun8i_hdmi_phy_init_a83t()
424 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
429 * Set PHY I2C address. It must match to the address set by in sun8i_hdmi_phy_init_a83t()
432 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
437 static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_h3() argument
441 sun8i_hdmi_phy_unlock(phy); in sun8i_hdmi_phy_init_h3()
443 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0); in sun8i_hdmi_phy_init_h3()
444 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
448 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
451 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
455 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
459 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
463 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
467 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
470 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
479 regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val, in sun8i_hdmi_phy_init_h3()
483 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
486 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
497 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, in sun8i_hdmi_phy_init_h3()
503 /* reset PHY PLL clock parent */ in sun8i_hdmi_phy_init_h3()
504 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_init_h3()
508 regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); in sun8i_hdmi_phy_init_h3()
511 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_hdmi_phy_init_h3()
512 phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; in sun8i_hdmi_phy_init_h3()
515 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init() argument
517 phy->variant->phy_init(phy); in sun8i_hdmi_phy_init()
520 void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_ops() argument
523 struct sun8i_hdmi_phy_variant *variant = phy->variant; in sun8i_hdmi_phy_set_ops()
528 plat_data->phy_data = phy; in sun8i_hdmi_phy_set_ops()
541 .name = "phy"
585 .compatible = "allwinner,sun8i-a83t-hdmi-phy",
589 .compatible = "allwinner,sun8i-h3-hdmi-phy",
593 .compatible = "allwinner,sun8i-r40-hdmi-phy",
597 .compatible = "allwinner,sun50i-a64-hdmi-phy",
601 .compatible = "allwinner,sun50i-h6-hdmi-phy",
611 struct sun8i_hdmi_phy *phy; in sun8i_hdmi_phy_probe() local
618 dev_err(dev, "Incompatible HDMI PHY\n"); in sun8i_hdmi_phy_probe()
622 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in sun8i_hdmi_phy_probe()
623 if (!phy) in sun8i_hdmi_phy_probe()
626 phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; in sun8i_hdmi_phy_probe()
630 dev_err(dev, "phy: Couldn't get our resources\n"); in sun8i_hdmi_phy_probe()
636 dev_err(dev, "Couldn't map the HDMI PHY registers\n"); in sun8i_hdmi_phy_probe()
640 phy->regs = devm_regmap_init_mmio(dev, regs, in sun8i_hdmi_phy_probe()
642 if (IS_ERR(phy->regs)) { in sun8i_hdmi_phy_probe()
643 dev_err(dev, "Couldn't create the HDMI PHY regmap\n"); in sun8i_hdmi_phy_probe()
644 return PTR_ERR(phy->regs); in sun8i_hdmi_phy_probe()
647 phy->clk_bus = of_clk_get_by_name(node, "bus"); in sun8i_hdmi_phy_probe()
648 if (IS_ERR(phy->clk_bus)) { in sun8i_hdmi_phy_probe()
650 return PTR_ERR(phy->clk_bus); in sun8i_hdmi_phy_probe()
653 phy->clk_mod = of_clk_get_by_name(node, "mod"); in sun8i_hdmi_phy_probe()
654 if (IS_ERR(phy->clk_mod)) { in sun8i_hdmi_phy_probe()
656 ret = PTR_ERR(phy->clk_mod); in sun8i_hdmi_phy_probe()
660 if (phy->variant->has_phy_clk) { in sun8i_hdmi_phy_probe()
661 phy->clk_pll0 = of_clk_get_by_name(node, "pll-0"); in sun8i_hdmi_phy_probe()
662 if (IS_ERR(phy->clk_pll0)) { in sun8i_hdmi_phy_probe()
664 ret = PTR_ERR(phy->clk_pll0); in sun8i_hdmi_phy_probe()
668 if (phy->variant->has_second_pll) { in sun8i_hdmi_phy_probe()
669 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); in sun8i_hdmi_phy_probe()
670 if (IS_ERR(phy->clk_pll1)) { in sun8i_hdmi_phy_probe()
672 ret = PTR_ERR(phy->clk_pll1); in sun8i_hdmi_phy_probe()
678 phy->rst_phy = of_reset_control_get_shared(node, "phy"); in sun8i_hdmi_phy_probe()
679 if (IS_ERR(phy->rst_phy)) { in sun8i_hdmi_phy_probe()
680 dev_err(dev, "Could not get phy reset control\n"); in sun8i_hdmi_phy_probe()
681 ret = PTR_ERR(phy->rst_phy); in sun8i_hdmi_phy_probe()
685 ret = reset_control_deassert(phy->rst_phy); in sun8i_hdmi_phy_probe()
687 dev_err(dev, "Cannot deassert phy reset control: %d\n", ret); in sun8i_hdmi_phy_probe()
691 ret = clk_prepare_enable(phy->clk_bus); in sun8i_hdmi_phy_probe()
697 ret = clk_prepare_enable(phy->clk_mod); in sun8i_hdmi_phy_probe()
703 if (phy->variant->has_phy_clk) { in sun8i_hdmi_phy_probe()
704 ret = sun8i_phy_clk_create(phy, dev, in sun8i_hdmi_phy_probe()
705 phy->variant->has_second_pll); in sun8i_hdmi_phy_probe()
707 dev_err(dev, "Couldn't create the PHY clock\n"); in sun8i_hdmi_phy_probe()
711 clk_prepare_enable(phy->clk_phy); in sun8i_hdmi_phy_probe()
714 hdmi->phy = phy; in sun8i_hdmi_phy_probe()
719 clk_disable_unprepare(phy->clk_mod); in sun8i_hdmi_phy_probe()
721 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_probe()
723 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_probe()
725 reset_control_put(phy->rst_phy); in sun8i_hdmi_phy_probe()
727 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_probe()
729 clk_put(phy->clk_pll0); in sun8i_hdmi_phy_probe()
731 clk_put(phy->clk_mod); in sun8i_hdmi_phy_probe()
733 clk_put(phy->clk_bus); in sun8i_hdmi_phy_probe()
740 struct sun8i_hdmi_phy *phy = hdmi->phy; in sun8i_hdmi_phy_remove() local
742 clk_disable_unprepare(phy->clk_mod); in sun8i_hdmi_phy_remove()
743 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_remove()
744 clk_disable_unprepare(phy->clk_phy); in sun8i_hdmi_phy_remove()
746 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_remove()
748 reset_control_put(phy->rst_phy); in sun8i_hdmi_phy_remove()
750 clk_put(phy->clk_pll0); in sun8i_hdmi_phy_remove()
751 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_remove()
752 clk_put(phy->clk_mod); in sun8i_hdmi_phy_remove()
753 clk_put(phy->clk_bus); in sun8i_hdmi_phy_remove()