378 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_phy_init()
386 		DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");  in dw_mipi_dsi_phy_init()
490 		DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
503 			DRM_DEV_ERROR(dsi->dev,  in dw_mipi_dsi_get_lane_mbps()
555 		DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");  in dw_mipi_dsi_get_lane_mbps()
638 		DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);  in dw_mipi_dsi_encoder_enable()
771 			DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");  in dw_mipi_dsi_rockchip_bind()
776 			DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");  in dw_mipi_dsi_rockchip_bind()
788 			DRM_DEV_ERROR(dev, "could not get slaves data\n");  in dw_mipi_dsi_rockchip_bind()
799 		DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);  in dw_mipi_dsi_rockchip_bind()
805 		DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");  in dw_mipi_dsi_rockchip_bind()
811 		DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);  in dw_mipi_dsi_rockchip_bind()
846 		DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",  in dw_mipi_dsi_rockchip_host_attach()
857 			DRM_DEV_ERROR(second,  in dw_mipi_dsi_rockchip_host_attach()
904 		DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");  in dw_mipi_dsi_rockchip_probe()
926 		DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()
935 			DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()
945 			DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);  in dw_mipi_dsi_rockchip_probe()
952 		DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");  in dw_mipi_dsi_rockchip_probe()
968 			DRM_DEV_ERROR(dev,  in dw_mipi_dsi_rockchip_probe()