Lines Matching refs:vddc
1775 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1780 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1789 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1792 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1794 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1813 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1816 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1820 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1822 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2295 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2352 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2356 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2361 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2365 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2551 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2552 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2553 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2554 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2976 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules() local
3032 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3033 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3041 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3042 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3091 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3094 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3107 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3118 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3124 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3125 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3153 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3154 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3157 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3163 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3166 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3171 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3172 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3178 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3236 u16 vddc, count = 0; in si_get_leakage_vddc() local
3240 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3242 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3243 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4170 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4182 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4185 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4192 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4421 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4422 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4428 &table->initialState.levels[0].vddc, in si_populate_smc_initial_state()
4432 table->initialState.levels[0].vddc.index, in si_populate_smc_initial_state()
4445 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4448 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4515 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4520 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4523 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4534 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4538 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4543 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4547 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4561 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4652 state->levels[0].std_vddc = state->levels[0].vddc; in si_populate_ulv_state()
4759 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5047 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5052 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5057 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5071 pl->vddc, in si_convert_power_level_to_smc()
5074 &level->vddc); in si_convert_power_level_to_smc()
5163 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5300 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5673 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6751 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6760 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6763 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6766 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6782 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6783 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6785 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6786 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6790 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
6791 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6794 pl->vddc = vddc; in si_parse_pplib_clock_info()
6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7109 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()