1871 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_powertune_defaults()  local
1875 		si_pi->cac_weights = cac_weights_tahiti;  in si_initialize_powertune_defaults()
1876 		si_pi->lcac_config = lcac_tahiti;  in si_initialize_powertune_defaults()
1877 		si_pi->cac_override = cac_override_tahiti;  in si_initialize_powertune_defaults()
1878 		si_pi->powertune_data = &powertune_data_tahiti;  in si_initialize_powertune_defaults()
1879 		si_pi->dte_data = dte_data_tahiti;  in si_initialize_powertune_defaults()
1883 			si_pi->dte_data.enable_dte_by_default = true;  in si_initialize_powertune_defaults()
1886 			si_pi->dte_data = dte_data_new_zealand;  in si_initialize_powertune_defaults()
1892 			si_pi->dte_data = dte_data_aruba_pro;  in si_initialize_powertune_defaults()
1896 			si_pi->dte_data = dte_data_malta;  in si_initialize_powertune_defaults()
1900 			si_pi->dte_data = dte_data_tahiti_pro;  in si_initialize_powertune_defaults()
1904 			if (si_pi->dte_data.enable_dte_by_default == true)  in si_initialize_powertune_defaults()
1912 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1913 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1914 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1915 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1916 			si_pi->dte_data = dte_data_curacao_xt;  in si_initialize_powertune_defaults()
1921 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1922 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1923 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1924 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1925 			si_pi->dte_data = dte_data_curacao_pro;  in si_initialize_powertune_defaults()
1930 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1931 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1932 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1933 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1934 			si_pi->dte_data = dte_data_neptune_xt;  in si_initialize_powertune_defaults()
1938 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1939 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1940 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1941 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1942 			si_pi->dte_data = dte_data_pitcairn;  in si_initialize_powertune_defaults()
1946 		si_pi->lcac_config = lcac_cape_verde;  in si_initialize_powertune_defaults()
1947 		si_pi->cac_override = cac_override_cape_verde;  in si_initialize_powertune_defaults()
1948 		si_pi->powertune_data = &powertune_data_cape_verde;  in si_initialize_powertune_defaults()
1955 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1956 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1959 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1960 			si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
1965 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1966 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1970 			si_pi->cac_weights = cac_weights_chelsea_xt;  in si_initialize_powertune_defaults()
1971 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1974 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1975 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1978 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1979 			si_pi->dte_data = dte_data_venus_xtx;  in si_initialize_powertune_defaults()
1982 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1983 			si_pi->dte_data = dte_data_venus_xt;  in si_initialize_powertune_defaults()
1989 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1990 			si_pi->dte_data = dte_data_venus_pro;  in si_initialize_powertune_defaults()
1993 			si_pi->cac_weights = cac_weights_cape_verde;  in si_initialize_powertune_defaults()
1994 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2003 			si_pi->cac_weights = cac_weights_mars_pro;  in si_initialize_powertune_defaults()
2004 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2005 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2006 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2007 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2014 			si_pi->cac_weights = cac_weights_mars_xt;  in si_initialize_powertune_defaults()
2015 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2016 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2017 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2018 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2024 			si_pi->cac_weights = cac_weights_oland_pro;  in si_initialize_powertune_defaults()
2025 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2026 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2027 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2028 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2032 			si_pi->cac_weights = cac_weights_oland_xt;  in si_initialize_powertune_defaults()
2033 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2034 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2035 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2036 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2040 			si_pi->cac_weights = cac_weights_oland;  in si_initialize_powertune_defaults()
2041 			si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2042 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2043 			si_pi->powertune_data = &powertune_data_oland;  in si_initialize_powertune_defaults()
2044 			si_pi->dte_data = dte_data_oland;  in si_initialize_powertune_defaults()
2048 		si_pi->cac_weights = cac_weights_hainan;  in si_initialize_powertune_defaults()
2049 		si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2050 		si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2051 		si_pi->powertune_data = &powertune_data_hainan;  in si_initialize_powertune_defaults()
2052 		si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
2062 	si_pi->enable_dte = false;  in si_initialize_powertune_defaults()
2064 	if (si_pi->powertune_data->enable_powertune_by_default) {  in si_initialize_powertune_defaults()
2067 		if (si_pi->dte_data.enable_dte_by_default) {  in si_initialize_powertune_defaults()
2068 			si_pi->enable_dte = true;  in si_initialize_powertune_defaults()
2070 				si_update_dte_from_pl2(rdev, &si_pi->dte_data);  in si_initialize_powertune_defaults()
2081 		si_pi->dyn_powertune_data.l2_lta_window_size =  in si_initialize_powertune_defaults()
2082 			si_pi->powertune_data->l2_lta_window_size_default;  in si_initialize_powertune_defaults()
2083 		si_pi->dyn_powertune_data.lts_truncate =  in si_initialize_powertune_defaults()
2084 			si_pi->powertune_data->lts_truncate_default;  in si_initialize_powertune_defaults()
2087 		si_pi->dyn_powertune_data.l2_lta_window_size = 0;  in si_initialize_powertune_defaults()
2088 		si_pi->dyn_powertune_data.lts_truncate = 0;  in si_initialize_powertune_defaults()
2091 	si_pi->dyn_powertune_data.disable_uvd_powertune = false;  in si_initialize_powertune_defaults()
2161 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits()  local
2164 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits()
2193 					   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +  in si_populate_smc_tdp_limits()
2197 					   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2201 		if (si_pi->enable_ppm) {  in si_populate_smc_tdp_limits()
2202 			papm_parm = &si_pi->papm_parm;  in si_populate_smc_tdp_limits()
2211 			ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,  in si_populate_smc_tdp_limits()
2214 						   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2226 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits_2()  local
2229 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits_2()
2241 					   (si_pi->state_table_start +  in si_populate_smc_tdp_limits_2()
2246 					   si_pi->sram_end);  in si_populate_smc_tdp_limits_2()
2279 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_should_disable_uvd_powertune()  local
2281 	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&  in si_should_disable_uvd_powertune()
2471 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_dte_tables()  local
2473 	struct si_dte_data *dte_data = &si_pi->dte_data;  in si_initialize_smc_dte_tables()
2480 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2482 	if (si_pi->enable_dte == false)  in si_initialize_smc_dte_tables()
2490 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2527 	ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,  in si_initialize_smc_dte_tables()
2528 				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);  in si_initialize_smc_dte_tables()
2537 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_cac_std_voltage_max_min()  local
2557 	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)  in si_get_cac_std_voltage_max_min()
2560 	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;  in si_get_cac_std_voltage_max_min()
2584 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_dte_leakage_table()  local
2601 							 &si_pi->powertune_data->leakage_coefficients,  in si_init_dte_leakage_table()
2604 							 si_pi->dyn_powertune_data.cac_leakage,  in si_init_dte_leakage_table()
2623 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_simplified_leakage_table()  local
2636 					   &si_pi->powertune_data->leakage_coefficients,  in si_init_simplified_leakage_table()
2637 					   si_pi->powertune_data->fixed_kt,  in si_init_simplified_leakage_table()
2639 					   si_pi->dyn_powertune_data.cac_leakage,  in si_init_simplified_leakage_table()
2657 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_cac_tables()  local
2673 	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);  in si_initialize_smc_cac_tables()
2676 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2677 	si_pi->dyn_powertune_data.dc_pwr_value =  in si_initialize_smc_cac_tables()
2678 		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];  in si_initialize_smc_cac_tables()
2679 	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);  in si_initialize_smc_cac_tables()
2680 	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;  in si_initialize_smc_cac_tables()
2682 	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;  in si_initialize_smc_cac_tables()
2693 	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)  in si_initialize_smc_cac_tables()
2705 	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);  in si_initialize_smc_cac_tables()
2706 	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;  in si_initialize_smc_cac_tables()
2707 	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;  in si_initialize_smc_cac_tables()
2711 	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);  in si_initialize_smc_cac_tables()
2715 	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;  in si_initialize_smc_cac_tables()
2719 	ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,  in si_initialize_smc_cac_tables()
2720 				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);  in si_initialize_smc_cac_tables()
2780 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_hardware_cac_manager()  local
2787 	ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);  in si_initialize_hardware_cac_manager()
2790 	ret = si_program_cac_config_registers(rdev, si_pi->cac_override);  in si_initialize_hardware_cac_manager()
2793 	ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);  in si_initialize_hardware_cac_manager()
2805 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_enable_smc_cac()  local
2826 				if (si_pi->enable_dte) {  in si_enable_smc_cac()
2833 			if (si_pi->enable_dte)  in si_enable_smc_cac()
2850 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_spll_table()  local
2860 	if (si_pi->spll_table_start == 0)  in si_init_smc_spll_table()
2906 		ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,  in si_init_smc_spll_table()
2908 					   si_pi->sram_end);  in si_init_smc_spll_table()
2922 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_lower_of_leakage_and_vce_voltage()  local
2925 	for (i = 0; i < si_pi->leakage_voltage.count; i++){  in si_get_lower_of_leakage_and_vce_voltage()
2926 		if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)  in si_get_lower_of_leakage_and_vce_voltage()
2927 			highest_leakage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_lower_of_leakage_and_vce_voltage()
2930 	if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))  in si_get_lower_of_leakage_and_vce_voltage()
3187 	struct si_power_info *si_pi = si_get_pi(rdev);
3190 				      si_pi->soft_regs_start + reg_offset, value,
3191 				      si_pi->sram_end);
3198 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_write_smc_soft_register()  local
3201 				       si_pi->soft_regs_start + reg_offset,  in si_write_smc_soft_register()
3202 				       value, si_pi->sram_end);  in si_write_smc_soft_register()
3235 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_vddc()  local
3243 			si_pi->leakage_voltage.entries[count].voltage = vddc;  in si_get_leakage_vddc()
3244 			si_pi->leakage_voltage.entries[count].leakage_index =  in si_get_leakage_vddc()
3249 	si_pi->leakage_voltage.count = count;  in si_get_leakage_vddc()
3255 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_voltage_from_leakage_index()  local
3270 	for (i = 0; i < si_pi->leakage_voltage.count; i++) {  in si_get_leakage_voltage_from_leakage_index()
3271 		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {  in si_get_leakage_voltage_from_leakage_index()
3272 			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_leakage_voltage_from_leakage_index()
3480 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_process_firmware_header()  local
3487 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3491 	si_pi->state_table_start = tmp;  in si_process_firmware_header()
3496 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3500 	si_pi->soft_regs_start = tmp;  in si_process_firmware_header()
3505 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3509 	si_pi->mc_reg_table_start = tmp;  in si_process_firmware_header()
3514 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3518 	si_pi->fan_table_start = tmp;  in si_process_firmware_header()
3523 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3527 	si_pi->arb_table_start = tmp;  in si_process_firmware_header()
3532 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3536 	si_pi->cac_table_start = tmp;  in si_process_firmware_header()
3541 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3545 	si_pi->dte_table_start = tmp;  in si_process_firmware_header()
3550 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3554 	si_pi->spll_table_start = tmp;  in si_process_firmware_header()
3559 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3563 	si_pi->papm_cfg_table_start = tmp;  in si_process_firmware_header()
3570 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_read_clock_registers()  local
3572 	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in si_read_clock_registers()
3573 	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3574 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in si_read_clock_registers()
3575 	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in si_read_clock_registers()
3576 	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in si_read_clock_registers()
3577 	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in si_read_clock_registers()
3578 	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in si_read_clock_registers()
3579 	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in si_read_clock_registers()
3580 	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in si_read_clock_registers()
3581 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in si_read_clock_registers()
3582 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in si_read_clock_registers()
3583 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in si_read_clock_registers()
3584 	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3585 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in si_read_clock_registers()
3586 	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in si_read_clock_registers()
3882 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_firmware()  local
3888 	ret = si_load_smc_ucode(rdev, si_pi->sram_end);  in si_upload_firmware()
3962 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_construct_voltage_tables()  local
3975 	} else if (si_pi->voltage_control_svi2) {  in si_construct_voltage_tables()
3996 	if (si_pi->vddci_control_svi2) {  in si_construct_voltage_tables()
4006 						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4013 		if (si_pi->mvdd_voltage_table.count == 0) {  in si_construct_voltage_tables()
4018 		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)  in si_construct_voltage_tables()
4021 								 &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4024 	if (si_pi->vddc_phase_shed_control) {  in si_construct_voltage_tables()
4026 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);  in si_construct_voltage_tables()
4028 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4030 		if ((si_pi->vddc_phase_shed_table.count == 0) ||  in si_construct_voltage_tables()
4031 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))  in si_construct_voltage_tables()
4032 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4053 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_voltage_tables()  local
4056 	if (si_pi->voltage_control_svi2) {  in si_populate_smc_voltage_tables()
4058 			si_pi->svc_gpio_id);  in si_populate_smc_voltage_tables()
4060 			si_pi->svd_gpio_id);  in si_populate_smc_voltage_tables()
4085 		if (si_pi->mvdd_voltage_table.count) {  in si_populate_smc_voltage_tables()
4086 			si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);  in si_populate_smc_voltage_tables()
4089 				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);  in si_populate_smc_voltage_tables()
4092 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_voltage_tables()
4093 			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,  in si_populate_smc_voltage_tables()
4095 				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);  in si_populate_smc_voltage_tables()
4098 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);  in si_populate_smc_voltage_tables()
4101 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);  in si_populate_smc_voltage_tables()
4103 				si_pi->vddc_phase_shed_control = false;  in si_populate_smc_voltage_tables()
4135 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mvdd_value()  local
4141 			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;  in si_populate_mvdd_value()
4143 		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);  in si_populate_mvdd_value()
4230 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_arb_table_index()  local
4234 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);  in si_init_arb_table_index()
4241 	return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);  in si_init_arb_table_index()
4257 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_force_switch_to_arb_f0()  local
4261 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,  in si_force_switch_to_arb_f0()
4262 				     &tmp, si_pi->sram_end);  in si_force_switch_to_arb_f0()
4323 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_do_program_memory_timing_parameters()  local
4333 					   si_pi->arb_table_start +  in si_do_program_memory_timing_parameters()
4338 					   si_pi->sram_end);  in si_do_program_memory_timing_parameters()
4357 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_initial_mvdd_value()  local
4360 		return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,  in si_populate_initial_mvdd_value()
4361 						 si_pi->mvdd_bootup_value, voltage);  in si_populate_initial_mvdd_value()
4373 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_initial_state()  local
4378 		cpu_to_be32(si_pi->clock_registers.dll_cntl);  in si_populate_smc_initial_state()
4380 		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);  in si_populate_smc_initial_state()
4382 		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);  in si_populate_smc_initial_state()
4384 		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);  in si_populate_smc_initial_state()
4386 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);  in si_populate_smc_initial_state()
4388 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);  in si_populate_smc_initial_state()
4390 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);  in si_populate_smc_initial_state()
4392 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_initial_state()
4394 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_initial_state()
4400 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);  in si_populate_smc_initial_state()
4402 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);  in si_populate_smc_initial_state()
4404 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);  in si_populate_smc_initial_state()
4406 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);  in si_populate_smc_initial_state()
4408 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);  in si_populate_smc_initial_state()
4410 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);  in si_populate_smc_initial_state()
4442 	if (si_pi->vddc_phase_shed_control)  in si_populate_smc_initial_state()
4457 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;  in si_populate_smc_initial_state()
4494 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_acpi_state()  local
4495 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_populate_smc_acpi_state()
4496 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_populate_smc_acpi_state()
4497 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_populate_smc_acpi_state()
4498 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_populate_smc_acpi_state()
4499 	u32 dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_smc_acpi_state()
4500 	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_smc_acpi_state()
4501 	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_smc_acpi_state()
4502 	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_smc_acpi_state()
4503 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_smc_acpi_state()
4504 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_smc_acpi_state()
4505 	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_smc_acpi_state()
4526 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;  in si_populate_smc_acpi_state()
4528 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_acpi_state()
4551 										    si_pi->sys_pcie_mask,  in si_populate_smc_acpi_state()
4552 										    si_pi->boot_pcie_gen,  in si_populate_smc_acpi_state()
4555 		if (si_pi->vddc_phase_shed_control)  in si_populate_smc_acpi_state()
4594 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_acpi_state()
4596 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_acpi_state()
4634 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_ulv_state()  local
4635 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()
4663 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_program_ulv_memory_timing_parameters()  local
4664 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()
4677 				   si_pi->arb_table_start +  in si_program_ulv_memory_timing_parameters()
4682 				   si_pi->sram_end);  in si_program_ulv_memory_timing_parameters()
4697 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_table()  local
4699 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()
4700 	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;  in si_init_smc_table()
4777 	return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,  in si_init_smc_table()
4779 				    si_pi->sram_end);  in si_init_smc_table()
4787 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_calculate_sclk_params()  local
4789 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_calculate_sclk_params()
4790 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_calculate_sclk_params()
4791 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_calculate_sclk_params()
4792 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_calculate_sclk_params()
4793 	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;  in si_calculate_sclk_params()
4794 	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
4881 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mclk_value()  local
4882 	u32  dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_mclk_value()
4883 	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_mclk_value()
4884 	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_mclk_value()
4885 	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_mclk_value()
4886 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_mclk_value()
4887 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_mclk_value()
4888 	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_mclk_value()
4889 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;  in si_populate_mclk_value()
4890 	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;  in si_populate_mclk_value()
4983 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_level_to_smc()  local
4990 	    (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))  in si_convert_power_level_to_smc()
4991 		level->gen2PCIE = (u8)si_pi->force_pcie_gen;  in si_convert_power_level_to_smc()
5068 	if (si_pi->vddc_phase_shed_control) {  in si_convert_power_level_to_smc()
5079 	level->MaxPoweredUpCU = si_pi->max_cu;  in si_convert_power_level_to_smc()
5137 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_disable_ulv()  local
5138 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()
5150 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_is_state_ulv_compatible()  local
5151 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()
5178 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_power_state_conditionally_enable_ulv()  local
5179 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()
5195 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_state_to_smc()  local
5220 			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {  in si_convert_power_state_to_smc()
5272 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_sw_state()  local
5275 	u32 address = si_pi->state_table_start +  in si_upload_sw_state()
5280 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()
5289 				   state_size, si_pi->sram_end);  in si_upload_sw_state()
5296 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_ulv_state()  local
5297 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()
5301 		u32 address = si_pi->state_table_start +  in si_upload_ulv_state()
5303 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()
5311 						   state_size, si_pi->sram_end);  in si_upload_ulv_state()
5535 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_mc_reg_table()  local
5537 	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;  in si_initialize_mc_reg_table()
5586 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_addresses()  local
5589 	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {  in si_populate_mc_reg_addresses()
5590 		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {  in si_populate_mc_reg_addresses()
5594 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);  in si_populate_mc_reg_addresses()
5596 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);  in si_populate_mc_reg_addresses()
5621 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_mc_reg_table_entry_to_smc()  local
5624 	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {  in si_convert_mc_reg_table_entry_to_smc()
5625 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in si_convert_mc_reg_table_entry_to_smc()
5629 	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))  in si_convert_mc_reg_table_entry_to_smc()
5632 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],  in si_convert_mc_reg_table_entry_to_smc()
5633 				mc_reg_table_data, si_pi->mc_reg_table.last,  in si_convert_mc_reg_table_entry_to_smc()
5634 				si_pi->mc_reg_table.valid_flag);  in si_convert_mc_reg_table_entry_to_smc()
5655 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_table()  local
5656 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()
5657 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_populate_mc_reg_table()
5668 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5670 				si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5671 				si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5677 		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5679 					si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5680 					si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5684 	return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,  in si_populate_mc_reg_table()
5686 				    sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);  in si_populate_mc_reg_table()
5693 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_mc_reg_table()  local
5694 	u32 address = si_pi->mc_reg_table_start +  in si_upload_mc_reg_table()
5697 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_upload_mc_reg_table()
5707 				    si_pi->sram_end);  in si_upload_mc_reg_table()
5748 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_request_link_speed_change_before_state_change()  local
5752 	if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)  in si_request_link_speed_change_before_state_change()
5755 		current_link_speed = si_pi->force_pcie_gen;  in si_request_link_speed_change_before_state_change()
5757 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_request_link_speed_change_before_state_change()
5758 	si_pi->pspp_notify_required = false;  in si_request_link_speed_change_before_state_change()
5765 			si_pi->force_pcie_gen = RADEON_PCIE_GEN2;  in si_request_link_speed_change_before_state_change()
5775 			si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);  in si_request_link_speed_change_before_state_change()
5780 			si_pi->pspp_notify_required = true;  in si_request_link_speed_change_before_state_change()
5788 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_notify_link_speed_change_after_state_change()  local
5792 	if (si_pi->pspp_notify_required) {  in si_notify_link_speed_change_after_state_change()
5831 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_max_cu_value()  local
5840 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5846 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5854 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5859 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5862 			si_pi->max_cu = 0;  in si_set_max_cu_value()
5866 		si_pi->max_cu = 0;  in si_set_max_cu_value()
6010 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_static_mode()  local
6013 	if (si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_static_mode()
6015 		si_pi->fan_ctrl_default_mode = tmp;  in si_fan_ctrl_set_static_mode()
6017 		si_pi->t_min = tmp;  in si_fan_ctrl_set_static_mode()
6018 		si_pi->fan_ctrl_is_in_default_mode = false;  in si_fan_ctrl_set_static_mode()
6032 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_thermal_setup_fan_table()  local
6041 	if (!si_pi->fan_table_start) {  in si_thermal_setup_fan_table()
6094 				   si_pi->fan_table_start,  in si_thermal_setup_fan_table()
6097 				   si_pi->sram_end);  in si_thermal_setup_fan_table()
6109 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_start_smc_fan_control()  local
6114 		si_pi->fan_is_controlled_by_smc = true;  in si_fan_ctrl_start_smc_fan_control()
6123 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_stop_smc_fan_control()  local
6129 		si_pi->fan_is_controlled_by_smc = false;  in si_fan_ctrl_stop_smc_fan_control()
6164 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_fan_speed_percent()  local
6172 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_set_fan_speed_percent()
6212 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_get_mode()  local
6215 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_get_mode()
6276 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_default_mode()  local
6279 	if (!si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_default_mode()
6281 		tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);  in si_fan_ctrl_set_default_mode()
6285 		tmp |= TMIN(si_pi->t_min);  in si_fan_ctrl_set_default_mode()
6287 		si_pi->fan_ctrl_is_in_default_mode = true;  in si_fan_ctrl_set_default_mode()
6353 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_dpm_enable()  local
6359 	if (pi->voltage_control || si_pi->voltage_control_svi2)  in si_dpm_enable()
6363 	if (pi->voltage_control || si_pi->voltage_control_svi2) {  in si_dpm_enable()
6738 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_parse_pplib_clock_info()  local
6755 						 si_pi->sys_pcie_mask,  in si_parse_pplib_clock_info()
6756 						 si_pi->boot_pcie_gen,  in si_parse_pplib_clock_info()
6768 		si_pi->acpi_pcie_gen = pl->pcie_gen;  in si_parse_pplib_clock_info()
6774 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
6775 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6776 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
6777 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
6778 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
6779 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()
6796 		si_pi->mvdd_bootup_value = mvdd;  in si_parse_pplib_clock_info()
6905 	struct si_power_info *si_pi;  in si_dpm_init()  local
6911 	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);  in si_dpm_init()
6912 	if (si_pi == NULL)  in si_dpm_init()
6914 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6915 	ni_pi = &si_pi->ni;  in si_dpm_init()
6922 		si_pi->sys_pcie_mask = 0;  in si_dpm_init()
6925 			si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |  in si_dpm_init()
6929 			si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |  in si_dpm_init()
6932 			si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;  in si_dpm_init()
6934 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_dpm_init()
6935 	si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);  in si_dpm_init()
7006 		si_pi->voltage_control_svi2 =  in si_dpm_init()
7009 		if (si_pi->voltage_control_svi2)  in si_dpm_init()
7011 						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);  in si_dpm_init()
7022 		si_pi->vddci_control_svi2 =  in si_dpm_init()
7026 	si_pi->vddc_phase_shed_control =  in si_dpm_init()
7039 	si_pi->sclk_deep_sleep_above_low = false;  in si_dpm_init()
7056 	si_pi->sram_end = SMC_RAM_END;  in si_dpm_init()
7074 	si_pi->fan_ctrl_is_in_default_mode = true;  in si_dpm_init()