6524 	struct radeon_ps *new_ps = &requested_ps;  in si_dpm_pre_set_power_state()  local
6526 	ni_update_requested_ps(rdev, new_ps);  in si_dpm_pre_set_power_state()
6535 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in si_power_control_set_level()  local
6544 	ret = si_populate_smc_tdp_limits(rdev, new_ps);  in si_power_control_set_level()
6547 	ret = si_populate_smc_tdp_limits_2(rdev, new_ps);  in si_power_control_set_level()
6562 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_set_power_state()  local
6577 		si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6578 	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6579 	ret = si_enable_power_containment(rdev, new_ps, false);  in si_dpm_set_power_state()
6584 	ret = si_enable_smc_cac(rdev, new_ps, false);  in si_dpm_set_power_state()
6594 	ret = si_upload_sw_state(rdev, new_ps);  in si_dpm_set_power_state()
6610 		ret = si_upload_mc_reg_table(rdev, new_ps);  in si_dpm_set_power_state()
6616 	ret = si_program_memory_timing_parameters(rdev, new_ps);  in si_dpm_set_power_state()
6621 	si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6633 	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6634 	si_set_vce_clock(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6636 		si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);  in si_dpm_set_power_state()
6637 	ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);  in si_dpm_set_power_state()
6642 	ret = si_enable_smc_cac(rdev, new_ps, true);  in si_dpm_set_power_state()
6647 	ret = si_enable_power_containment(rdev, new_ps, true);  in si_dpm_set_power_state()
6665 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_post_set_power_state()  local
6667 	ni_update_current_ps(rdev, new_ps);  in si_dpm_post_set_power_state()