Lines Matching refs:tmp
199 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
202 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
204 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
392 uint32_t tmp; in radeon_legacy_set_engine_clock() local
399 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
400 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
401 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
403 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
404 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
405 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
409 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
410 tmp |= RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
411 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
415 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
416 tmp |= RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
417 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
421 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_set_engine_clock()
422 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); in radeon_legacy_set_engine_clock()
423 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; in radeon_legacy_set_engine_clock()
424 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
427 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
428 tmp &= ~RADEON_SPLL_PVG_MASK; in radeon_legacy_set_engine_clock()
430 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
432 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
433 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
435 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
436 tmp &= ~RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
437 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
441 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
442 tmp &= ~RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
443 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
447 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
448 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
452 tmp |= 1; in radeon_legacy_set_engine_clock()
455 tmp |= 2; in radeon_legacy_set_engine_clock()
458 tmp |= 3; in radeon_legacy_set_engine_clock()
461 tmp |= 4; in radeon_legacy_set_engine_clock()
464 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
468 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
469 tmp |= RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
470 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
477 uint32_t tmp; in radeon_legacy_set_clock_gating() local
481 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
485 tmp &= in radeon_legacy_set_clock_gating()
489 tmp &= in radeon_legacy_set_clock_gating()
495 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
499 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
500 tmp &= in radeon_legacy_set_clock_gating()
514 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
515 tmp |= in radeon_legacy_set_clock_gating()
518 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
520 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
521 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
522 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
523 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
525 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
526 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
528 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
530 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
531 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
544 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
546 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
547 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
550 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | in radeon_legacy_set_clock_gating()
553 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
555 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
556 tmp &= in radeon_legacy_set_clock_gating()
570 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
571 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
573 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
574 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
575 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
576 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
578 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
579 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
581 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
583 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
584 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
597 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
599 tmp = RREG32_PLL(RADEON_MCLK_MISC); in radeon_legacy_set_clock_gating()
600 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | in radeon_legacy_set_clock_gating()
602 WREG32_PLL(RADEON_MCLK_MISC, tmp); in radeon_legacy_set_clock_gating()
604 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
605 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
608 tmp &= ~(RADEON_FORCEON_YCLKA | in radeon_legacy_set_clock_gating()
616 if ((tmp & R300_DISABLE_MC_MCLKA) && in radeon_legacy_set_clock_gating()
617 (tmp & R300_DISABLE_MC_MCLKB)) { in radeon_legacy_set_clock_gating()
619 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
623 tmp &= in radeon_legacy_set_clock_gating()
626 tmp &= in radeon_legacy_set_clock_gating()
629 tmp &= ~(R300_DISABLE_MC_MCLKA | in radeon_legacy_set_clock_gating()
634 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
636 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
637 tmp &= ~(R300_SCLK_FORCE_VAP); in radeon_legacy_set_clock_gating()
638 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
639 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
642 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
643 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
646 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
649 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
651 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | in radeon_legacy_set_clock_gating()
655 tmp |= (RADEON_ENGIN_DYNCLK_MODE | in radeon_legacy_set_clock_gating()
657 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
660 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_clock_gating()
661 tmp |= RADEON_SCLK_DYN_START_CNTL; in radeon_legacy_set_clock_gating()
662 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_clock_gating()
668 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
670 tmp &= ~RADEON_SCLK_FORCEON_MASK; in radeon_legacy_set_clock_gating()
682 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
683 tmp |= RADEON_SCLK_FORCE_VIP; in radeon_legacy_set_clock_gating()
686 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
691 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
692 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
700 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
702 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
712 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
713 tmp |= RADEON_TCL_BYPASS_DISABLE; in radeon_legacy_set_clock_gating()
714 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
719 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
720 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
728 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
731 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
732 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
735 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
741 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
742 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
749 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
752 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
753 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
761 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
763 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
764 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
765 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
767 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
768 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
771 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
773 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
774 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
788 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
791 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
792 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
794 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
796 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
797 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
805 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
807 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
808 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
809 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
811 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
812 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
816 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
818 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
819 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
822 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
824 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
825 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
839 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
841 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
842 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); in radeon_legacy_set_clock_gating()
843 tmp |= RADEON_SCLK_FORCE_SE; in radeon_legacy_set_clock_gating()
846 tmp |= (RADEON_SCLK_FORCE_RB | in radeon_legacy_set_clock_gating()
859 tmp |= (RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
866 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
872 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
873 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
876 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
881 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
882 tmp &= ~(RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
884 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
891 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
892 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
893 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
897 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
898 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
906 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
909 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
910 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
912 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()