Lines Matching refs:rdev
45 void r420_pm_init_profile(struct radeon_device *rdev) in r420_pm_init_profile() argument
48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
51 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
56 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
61 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
66 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
71 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
76 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
81 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
84 static void r420_set_reg_safe(struct radeon_device *rdev) in r420_set_reg_safe() argument
86 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; in r420_set_reg_safe()
87 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); in r420_set_reg_safe()
90 void r420_pipes_init(struct radeon_device *rdev) in r420_pipes_init() argument
100 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
108 if ((rdev->pdev->device == 0x5e4c) || in r420_pipes_init()
109 (rdev->pdev->device == 0x5e4f)) in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
136 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
148 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
152 if (rdev->family == CHIP_RV530) { in r420_pipes_init()
155 rdev->num_z_pipes = 2; in r420_pipes_init()
157 rdev->num_z_pipes = 1; in r420_pipes_init()
159 rdev->num_z_pipes = 1; in r420_pipes_init()
162 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
165 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) in r420_mc_rreg() argument
170 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
173 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
177 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r420_mc_wreg() argument
181 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
185 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
188 static void r420_debugfs(struct radeon_device *rdev) in r420_debugfs() argument
190 if (r100_debugfs_rbbm_init(rdev)) { in r420_debugfs()
193 if (r420_debugfs_pipes_info_init(rdev)) { in r420_debugfs()
198 static void r420_clock_resume(struct radeon_device *rdev) in r420_clock_resume() argument
203 radeon_atom_set_clock_gating(rdev, 1); in r420_clock_resume()
206 if (rdev->family == CHIP_R420) in r420_clock_resume()
211 static void r420_cp_errata_init(struct radeon_device *rdev) in r420_cp_errata_init() argument
214 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
222 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
223 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_init()
226 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
228 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_init()
231 static void r420_cp_errata_fini(struct radeon_device *rdev) in r420_cp_errata_fini() argument
234 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
239 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_fini()
243 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_fini()
244 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
247 static int r420_startup(struct radeon_device *rdev) in r420_startup() argument
252 r100_set_common_regs(rdev); in r420_startup()
254 r300_mc_program(rdev); in r420_startup()
256 r420_clock_resume(rdev); in r420_startup()
259 if (rdev->flags & RADEON_IS_PCIE) { in r420_startup()
260 r = rv370_pcie_gart_enable(rdev); in r420_startup()
264 if (rdev->flags & RADEON_IS_PCI) { in r420_startup()
265 r = r100_pci_gart_enable(rdev); in r420_startup()
269 r420_pipes_init(rdev); in r420_startup()
272 r = radeon_wb_init(rdev); in r420_startup()
276 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
278 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r420_startup()
283 if (!rdev->irq.installed) { in r420_startup()
284 r = radeon_irq_kms_init(rdev); in r420_startup()
289 r100_irq_set(rdev); in r420_startup()
290 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
292 r = r100_cp_init(rdev, 1024 * 1024); in r420_startup()
294 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r420_startup()
297 r420_cp_errata_init(rdev); in r420_startup()
299 r = radeon_ib_pool_init(rdev); in r420_startup()
301 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r420_startup()
308 int r420_resume(struct radeon_device *rdev) in r420_resume() argument
313 if (rdev->flags & RADEON_IS_PCIE) in r420_resume()
314 rv370_pcie_gart_disable(rdev); in r420_resume()
315 if (rdev->flags & RADEON_IS_PCI) in r420_resume()
316 r100_pci_gart_disable(rdev); in r420_resume()
318 r420_clock_resume(rdev); in r420_resume()
320 if (radeon_asic_reset(rdev)) { in r420_resume()
321 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
326 if (rdev->is_atom_bios) { in r420_resume()
327 atom_asic_init(rdev->mode_info.atom_context); in r420_resume()
329 radeon_combios_asic_init(rdev->ddev); in r420_resume()
332 r420_clock_resume(rdev); in r420_resume()
334 radeon_surface_init(rdev); in r420_resume()
336 rdev->accel_working = true; in r420_resume()
337 r = r420_startup(rdev); in r420_resume()
339 rdev->accel_working = false; in r420_resume()
344 int r420_suspend(struct radeon_device *rdev) in r420_suspend() argument
346 radeon_pm_suspend(rdev); in r420_suspend()
347 r420_cp_errata_fini(rdev); in r420_suspend()
348 r100_cp_disable(rdev); in r420_suspend()
349 radeon_wb_disable(rdev); in r420_suspend()
350 r100_irq_disable(rdev); in r420_suspend()
351 if (rdev->flags & RADEON_IS_PCIE) in r420_suspend()
352 rv370_pcie_gart_disable(rdev); in r420_suspend()
353 if (rdev->flags & RADEON_IS_PCI) in r420_suspend()
354 r100_pci_gart_disable(rdev); in r420_suspend()
358 void r420_fini(struct radeon_device *rdev) in r420_fini() argument
360 radeon_pm_fini(rdev); in r420_fini()
361 r100_cp_fini(rdev); in r420_fini()
362 radeon_wb_fini(rdev); in r420_fini()
363 radeon_ib_pool_fini(rdev); in r420_fini()
364 radeon_gem_fini(rdev); in r420_fini()
365 if (rdev->flags & RADEON_IS_PCIE) in r420_fini()
366 rv370_pcie_gart_fini(rdev); in r420_fini()
367 if (rdev->flags & RADEON_IS_PCI) in r420_fini()
368 r100_pci_gart_fini(rdev); in r420_fini()
369 radeon_agp_fini(rdev); in r420_fini()
370 radeon_irq_kms_fini(rdev); in r420_fini()
371 radeon_fence_driver_fini(rdev); in r420_fini()
372 radeon_bo_fini(rdev); in r420_fini()
373 if (rdev->is_atom_bios) { in r420_fini()
374 radeon_atombios_fini(rdev); in r420_fini()
376 radeon_combios_fini(rdev); in r420_fini()
378 kfree(rdev->bios); in r420_fini()
379 rdev->bios = NULL; in r420_fini()
382 int r420_init(struct radeon_device *rdev) in r420_init() argument
387 radeon_scratch_init(rdev); in r420_init()
389 radeon_surface_init(rdev); in r420_init()
392 r100_restore_sanity(rdev); in r420_init()
394 if (!radeon_get_bios(rdev)) { in r420_init()
395 if (ASIC_IS_AVIVO(rdev)) in r420_init()
398 if (rdev->is_atom_bios) { in r420_init()
399 r = radeon_atombios_init(rdev); in r420_init()
404 r = radeon_combios_init(rdev); in r420_init()
410 if (radeon_asic_reset(rdev)) { in r420_init()
411 dev_warn(rdev->dev, in r420_init()
417 if (radeon_boot_test_post_card(rdev) == false) in r420_init()
421 radeon_get_clock_info(rdev->ddev); in r420_init()
423 if (rdev->flags & RADEON_IS_AGP) { in r420_init()
424 r = radeon_agp_init(rdev); in r420_init()
426 radeon_agp_disable(rdev); in r420_init()
430 r300_mc_init(rdev); in r420_init()
431 r420_debugfs(rdev); in r420_init()
433 r = radeon_fence_driver_init(rdev); in r420_init()
438 r = radeon_bo_init(rdev); in r420_init()
442 if (rdev->family == CHIP_R420) in r420_init()
443 r100_enable_bm(rdev); in r420_init()
445 if (rdev->flags & RADEON_IS_PCIE) { in r420_init()
446 r = rv370_pcie_gart_init(rdev); in r420_init()
450 if (rdev->flags & RADEON_IS_PCI) { in r420_init()
451 r = r100_pci_gart_init(rdev); in r420_init()
455 r420_set_reg_safe(rdev); in r420_init()
458 radeon_pm_init(rdev); in r420_init()
460 rdev->accel_working = true; in r420_init()
461 r = r420_startup(rdev); in r420_init()
464 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r420_init()
465 r100_cp_fini(rdev); in r420_init()
466 radeon_wb_fini(rdev); in r420_init()
467 radeon_ib_pool_fini(rdev); in r420_init()
468 radeon_irq_kms_fini(rdev); in r420_init()
469 if (rdev->flags & RADEON_IS_PCIE) in r420_init()
470 rv370_pcie_gart_fini(rdev); in r420_init()
471 if (rdev->flags & RADEON_IS_PCI) in r420_init()
472 r100_pci_gart_fini(rdev); in r420_init()
473 radeon_agp_fini(rdev); in r420_init()
474 rdev->accel_working = false; in r420_init()
487 struct radeon_device *rdev = dev->dev_private; in r420_debugfs_pipes_info() local
504 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) in r420_debugfs_pipes_info_init() argument
507 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); in r420_debugfs_pipes_info_init()