Lines Matching refs:pi
253 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
255 return pi; in kv_get_pi()
335 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
338 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
347 if (pi->caps_db_ramping) { in kv_do_enable_didt()
356 if (pi->caps_td_ramping) { in kv_do_enable_didt()
365 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
377 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
380 if (pi->caps_sq_ramping || in kv_enable_didt()
381 pi->caps_db_ramping || in kv_enable_didt()
382 pi->caps_td_ramping || in kv_enable_didt()
383 pi->caps_tcp_ramping) { in kv_enable_didt()
405 struct kv_power_info *pi = kv_get_pi(rdev);
407 if (pi->caps_cac) {
437 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_smc_cac() local
440 if (pi->caps_cac) { in kv_enable_smc_cac()
444 pi->cac_enabled = false; in kv_enable_smc_cac()
446 pi->cac_enabled = true; in kv_enable_smc_cac()
447 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
449 pi->cac_enabled = false; in kv_enable_smc_cac()
458 struct kv_power_info *pi = kv_get_pi(rdev); in kv_process_firmware_header() local
464 &tmp, pi->sram_end); in kv_process_firmware_header()
467 pi->dpm_table_start = tmp; in kv_process_firmware_header()
471 &tmp, pi->sram_end); in kv_process_firmware_header()
474 pi->soft_regs_start = tmp; in kv_process_firmware_header()
481 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_dpm_voltage_scaling() local
484 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
487 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
489 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
490 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
497 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_interval() local
500 pi->graphics_interval = 1; in kv_set_dpm_interval()
503 pi->dpm_table_start + in kv_set_dpm_interval()
505 &pi->graphics_interval, in kv_set_dpm_interval()
506 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
513 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_boot_state() local
517 pi->dpm_table_start + in kv_set_dpm_boot_state()
519 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
520 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
538 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_divider_value() local
547 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
548 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
608 struct kv_power_info *pi = kv_get_pi(rdev); in kv_convert_2bit_index_to_voltage() local
610 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
619 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_vid() local
621 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
622 pi->graphics_level[index].MinVddNb = in kv_set_vid()
630 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_at() local
632 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
640 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enable() local
642 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
700 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_sclk_t() local
704 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
705 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
708 pi->dpm_table_start + in kv_update_sclk_t()
711 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
718 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_bootup_state() local
724 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
725 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
729 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
733 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
738 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
739 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
743 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
751 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_auto_thermal_throttling() local
754 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
757 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
759 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
760 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
767 struct kv_power_info *pi = kv_get_pi(rdev); in kv_upload_dpm_settings() local
771 pi->dpm_table_start + in kv_upload_dpm_settings()
773 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
775 pi->sram_end); in kv_upload_dpm_settings()
781 pi->dpm_table_start + in kv_upload_dpm_settings()
783 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
784 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
796 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_clk_bypass() local
799 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
821 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_uvd_table() local
831 pi->uvd_level_count = 0; in kv_populate_uvd_table()
833 if (pi->high_voltage_t && in kv_populate_uvd_table()
834 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
837 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
838 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
839 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
841 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
843 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
850 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
856 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
858 pi->uvd_level_count++; in kv_populate_uvd_table()
862 pi->dpm_table_start + in kv_populate_uvd_table()
864 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
865 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
869 pi->uvd_interval = 1; in kv_populate_uvd_table()
872 pi->dpm_table_start + in kv_populate_uvd_table()
874 &pi->uvd_interval, in kv_populate_uvd_table()
875 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
880 pi->dpm_table_start + in kv_populate_uvd_table()
882 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
884 pi->sram_end); in kv_populate_uvd_table()
892 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_vce_table() local
902 pi->vce_level_count = 0; in kv_populate_vce_table()
904 if (pi->high_voltage_t && in kv_populate_vce_table()
905 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
908 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
909 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
911 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
918 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
920 pi->vce_level_count++; in kv_populate_vce_table()
924 pi->dpm_table_start + in kv_populate_vce_table()
926 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
928 pi->sram_end); in kv_populate_vce_table()
932 pi->vce_interval = 1; in kv_populate_vce_table()
935 pi->dpm_table_start + in kv_populate_vce_table()
937 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
939 pi->sram_end); in kv_populate_vce_table()
944 pi->dpm_table_start + in kv_populate_vce_table()
946 (u8 *)&pi->vce_level, in kv_populate_vce_table()
948 pi->sram_end); in kv_populate_vce_table()
955 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_samu_table() local
965 pi->samu_level_count = 0; in kv_populate_samu_table()
967 if (pi->high_voltage_t && in kv_populate_samu_table()
968 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
971 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
972 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
974 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
981 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
983 pi->samu_level_count++; in kv_populate_samu_table()
987 pi->dpm_table_start + in kv_populate_samu_table()
989 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
991 pi->sram_end); in kv_populate_samu_table()
995 pi->samu_interval = 1; in kv_populate_samu_table()
998 pi->dpm_table_start + in kv_populate_samu_table()
1000 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1002 pi->sram_end); in kv_populate_samu_table()
1007 pi->dpm_table_start + in kv_populate_samu_table()
1009 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1011 pi->sram_end); in kv_populate_samu_table()
1021 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_acp_table() local
1031 pi->acp_level_count = 0; in kv_populate_acp_table()
1033 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1034 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1040 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1042 pi->acp_level_count++; in kv_populate_acp_table()
1046 pi->dpm_table_start + in kv_populate_acp_table()
1048 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1050 pi->sram_end); in kv_populate_acp_table()
1054 pi->acp_interval = 1; in kv_populate_acp_table()
1057 pi->dpm_table_start + in kv_populate_acp_table()
1059 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1061 pi->sram_end); in kv_populate_acp_table()
1066 pi->dpm_table_start + in kv_populate_acp_table()
1068 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1070 pi->sram_end); in kv_populate_acp_table()
1079 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dfs_bypass_settings() local
1085 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1086 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1088 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1090 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1092 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1094 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1096 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1098 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1100 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1105 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1106 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1107 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1109 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1111 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1113 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1115 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1117 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1119 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1121 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1135 struct kv_power_info *pi = kv_get_pi(rdev); in kv_reset_acp_boot_level() local
1137 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1144 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_current_ps() local
1146 pi->current_rps = *rps; in kv_update_current_ps()
1147 pi->current_ps = *new_ps; in kv_update_current_ps()
1148 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1155 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_requested_ps() local
1157 pi->requested_rps = *rps; in kv_update_requested_ps()
1158 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1159 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1164 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable_bapm() local
1167 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1189 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable() local
1235 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1338 struct kv_power_info *pi = kv_get_pi(rdev);
1340 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1341 (u8 *)&value, sizeof(u16), pi->sram_end);
1347 struct kv_power_info *pi = kv_get_pi(rdev);
1349 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1350 value, pi->sram_end);
1356 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_sclk_t() local
1358 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1363 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_fps_limits() local
1366 if (pi->caps_fps) { in kv_init_fps_limits()
1370 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1372 pi->dpm_table_start + in kv_init_fps_limits()
1374 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1375 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1378 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1381 pi->dpm_table_start + in kv_init_fps_limits()
1383 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1384 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1392 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_powergate_state() local
1394 pi->uvd_power_gated = false; in kv_init_powergate_state()
1395 pi->vce_power_gated = false; in kv_init_powergate_state()
1396 pi->samu_power_gated = false; in kv_init_powergate_state()
1397 pi->acp_power_gated = false; in kv_init_powergate_state()
1427 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_uvd_dpm() local
1435 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1437 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1439 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1440 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1446 pi->dpm_table_start + in kv_update_uvd_dpm()
1448 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1449 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1479 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_vce_dpm() local
1488 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1489 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1491 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1494 pi->dpm_table_start + in kv_update_vce_dpm()
1496 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1498 pi->sram_end); in kv_update_vce_dpm()
1502 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1505 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1520 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_samu_dpm() local
1526 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1527 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1529 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1532 pi->dpm_table_start + in kv_update_samu_dpm()
1534 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1536 pi->sram_end); in kv_update_samu_dpm()
1540 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1543 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1568 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_boot_level() local
1571 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1573 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1574 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1577 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1584 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_dpm() local
1590 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1591 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1593 pi->acp_boot_level = kv_get_acp_boot_level(rdev); in kv_update_acp_dpm()
1596 pi->dpm_table_start + in kv_update_acp_dpm()
1598 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1600 pi->sram_end); in kv_update_acp_dpm()
1604 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1607 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1615 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_uvd() local
1617 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1620 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1623 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1628 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1631 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1643 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_vce() local
1645 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1648 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1651 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1656 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1666 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_samu() local
1668 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1671 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1675 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1678 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1686 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_acp() local
1688 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1694 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1698 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1701 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1711 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_valid_clock_range() local
1717 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1719 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1720 pi->lowest_valid = i; in kv_set_valid_clock_range()
1725 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1729 pi->highest_valid = i; in kv_set_valid_clock_range()
1731 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1732 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1733 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1734 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1736 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1740 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1742 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1744 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1745 pi->lowest_valid = i; in kv_set_valid_clock_range()
1750 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1755 pi->highest_valid = i; in kv_set_valid_clock_range()
1757 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1759 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1760 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1762 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1764 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1773 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_dfs_bypass_settings() local
1777 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1779 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1781 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1783 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1786 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1795 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_nb_dpm() local
1799 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1802 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1805 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1808 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1841 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_pre_set_power_state() local
1848 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1849 &pi->current_rps); in kv_dpm_pre_set_power_state()
1856 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_set_power_state() local
1857 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1858 struct radeon_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1861 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1870 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1899 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1930 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_post_set_power_state() local
1931 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
1946 struct kv_power_info *pi = kv_get_pi(rdev);
1961 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1971 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_max_power_limits_table() local
1973 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
1974 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
1976 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
1979 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
1982 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2029 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_boot_state() local
2031 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2032 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2033 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2034 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2035 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2036 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2037 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2038 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2084 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_sleep_divider_id_from_clock() local
2093 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2107 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_high_voltage_limit() local
2114 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2116 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2123 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2126 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2128 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2144 struct kv_power_info *pi = kv_get_pi(rdev); in kv_apply_state_adjust_rules() local
2166 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2196 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2197 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2205 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2208 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2209 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2217 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2223 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2228 pi->battery_state = true; in kv_apply_state_adjust_rules()
2230 pi->battery_state = false; in kv_apply_state_adjust_rules()
2243 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2244 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2245 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2246 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2258 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enabled_for_throttle() local
2260 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2265 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_ds_divider() local
2269 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2272 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2273 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2275 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2283 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_nbps_level_settings() local
2290 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2294 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2295 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2296 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2297 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2300 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2303 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2304 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2307 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2308 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2310 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2311 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2313 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2314 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2315 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2316 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2319 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2320 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2321 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2322 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2325 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2326 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2327 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2328 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2329 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2337 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dpm_settings() local
2340 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2343 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2344 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2351 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_graphics_levels() local
2359 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2361 if (pi->high_voltage_t && in kv_init_graphics_levels()
2362 (pi->high_voltage_t < in kv_init_graphics_levels()
2368 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2371 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2373 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2377 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2379 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2381 if (pi->high_voltage_t && in kv_init_graphics_levels()
2382 pi->high_voltage_t < in kv_init_graphics_levels()
2388 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2390 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2400 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_new_levels() local
2404 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2420 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_enabled_levels() local
2423 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2435 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_nbps_index_settings() local
2441 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2492 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_sys_info_table() local
2509 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2510 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2511 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2514 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2516 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2518 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2520 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2521 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2526 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2528 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2531 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2533 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2538 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2541 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2545 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2578 struct kv_power_info *pi = kv_get_pi(rdev); in kv_patch_boot_state() local
2581 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2615 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_pplib_clock_info() local
2627 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2725 struct kv_power_info *pi; in kv_dpm_init() local
2728 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2729 if (pi == NULL) in kv_dpm_init()
2731 rdev->pm.dpm.priv = pi; in kv_dpm_init()
2742 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2744 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2748 pi->enable_nb_dpm = false; in kv_dpm_init()
2750 pi->enable_nb_dpm = true; in kv_dpm_init()
2752 pi->caps_power_containment = true; in kv_dpm_init()
2753 pi->caps_cac = true; in kv_dpm_init()
2754 pi->enable_didt = false; in kv_dpm_init()
2755 if (pi->enable_didt) { in kv_dpm_init()
2756 pi->caps_sq_ramping = true; in kv_dpm_init()
2757 pi->caps_db_ramping = true; in kv_dpm_init()
2758 pi->caps_td_ramping = true; in kv_dpm_init()
2759 pi->caps_tcp_ramping = true; in kv_dpm_init()
2762 pi->caps_sclk_ds = true; in kv_dpm_init()
2763 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2764 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2768 pi->bapm_enable = true; in kv_dpm_init()
2770 pi->bapm_enable = false; in kv_dpm_init()
2772 pi->bapm_enable = false; in kv_dpm_init()
2774 pi->bapm_enable = true; in kv_dpm_init()
2776 pi->voltage_drop_t = 0; in kv_dpm_init()
2777 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2778 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2779 pi->caps_uvd_pg = true; in kv_dpm_init()
2780 pi->caps_uvd_dpm = true; in kv_dpm_init()
2781 pi->caps_vce_pg = false; /* XXX true */ in kv_dpm_init()
2782 pi->caps_samu_pg = false; in kv_dpm_init()
2783 pi->caps_acp_pg = false; in kv_dpm_init()
2784 pi->caps_stable_p_state = false; in kv_dpm_init()
2797 pi->enable_dpm = true; in kv_dpm_init()
2805 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_debugfs_print_current_performance_level() local
2815 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2819 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2820 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2828 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_sclk() local
2837 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_get_current_sclk()
2844 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_mclk() local
2846 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_current_mclk()
2886 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_sclk() local
2887 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2897 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_mclk() local
2899 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()