2804 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2829 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2830 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2837 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2838 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2848 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2850 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2871 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2872 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2878 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2880 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2898 					dst_offset = radeon_get_ib_value(p, idx + 7);  in evergreen_dma_cs_parse()
2899 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2909 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2910 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
2918 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2920 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2930 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2931 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2937 				if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2939 							dst_offset + count, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2970 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2971 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2981 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2983 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3010 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3011 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3021 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3023 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3072 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3073 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3083 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3085 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3109 					dst_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3110 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3120 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3121 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
3129 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3131 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3159 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3160 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3170 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3172 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3197 			dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3198 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in evergreen_dma_cs_parse()
3199 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3201 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()