Lines Matching refs:dst2_offset
2804 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2972 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2973 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2986 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
2988 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3012 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3013 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3026 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3028 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3074 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3075 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3088 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3090 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3161 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3162 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3175 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3177 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()